1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_aipstz.h> 26 #include <imx_uart.h> 27 #include <plat_imx8.h> 28 29 static const mmap_region_t imx_mmap[] = { 30 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 31 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 32 {0}, 33 }; 34 35 static const struct aipstz_cfg aipstz[] = { 36 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 37 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 38 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {0}, 41 }; 42 43 static entry_point_info_t bl32_image_ep_info; 44 static entry_point_info_t bl33_image_ep_info; 45 46 /* get SPSR for BL33 entry */ 47 static uint32_t get_spsr_for_bl33_entry(void) 48 { 49 unsigned long el_status; 50 unsigned long mode; 51 uint32_t spsr; 52 53 /* figure out what mode we enter the non-secure world */ 54 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 55 el_status &= ID_AA64PFR0_ELX_MASK; 56 57 mode = (el_status) ? MODE_EL2 : MODE_EL1; 58 59 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 60 return spsr; 61 } 62 63 void bl31_tzc380_setup(void) 64 { 65 unsigned int val; 66 67 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 68 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 69 return; 70 71 tzc380_init(IMX_TZASC_BASE); 72 73 /* 74 * Need to substact offset 0x40000000 from CPU address when 75 * programming tzasc region for i.mx8mm. 76 */ 77 78 /* Enable 1G-5G S/NS RW */ 79 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 80 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 81 } 82 83 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 84 u_register_t arg2, u_register_t arg3) 85 { 86 static console_uart_t console; 87 int i; 88 89 /* Enable CSU NS access permission */ 90 for (i = 0; i < 64; i++) { 91 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 92 } 93 94 imx_aipstz_init(aipstz); 95 96 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 97 IMX_CONSOLE_BAUDRATE, &console); 98 /* This console is only used for boot stage */ 99 console_set_scope(&console.console, CONSOLE_FLAG_BOOT); 100 101 /* 102 * tell BL3-1 where the non-secure software image is located 103 * and the entry state information. 104 */ 105 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 106 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 107 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 108 109 bl31_tzc380_setup(); 110 } 111 112 void bl31_plat_arch_setup(void) 113 { 114 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 115 MT_MEMORY | MT_RW | MT_SECURE); 116 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 117 MT_MEMORY | MT_RO | MT_SECURE); 118 #if USE_COHERENT_MEM 119 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 120 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 121 MT_DEVICE | MT_RW | MT_SECURE); 122 #endif 123 mmap_add(imx_mmap); 124 125 init_xlat_tables(); 126 127 enable_mmu_el3(0); 128 } 129 130 void bl31_platform_setup(void) 131 { 132 generic_delay_timer_init(); 133 134 /* select the CKIL source to 32K OSC */ 135 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 136 137 plat_gic_driver_init(); 138 plat_gic_init(); 139 140 imx_gpc_init(); 141 } 142 143 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 144 { 145 if (type == NON_SECURE) 146 return &bl33_image_ep_info; 147 if (type == SECURE) 148 return &bl32_image_ep_info; 149 150 return NULL; 151 } 152 153 unsigned int plat_get_syscnt_freq2(void) 154 { 155 return COUNTER_FREQUENCY; 156 } 157