1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_aipstz.h> 26 #include <imx_uart.h> 27 #include <imx_rdc.h> 28 #include <imx8m_caam.h> 29 #include <imx8m_csu.h> 30 #include <plat_imx8.h> 31 32 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 33 34 static const mmap_region_t imx_mmap[] = { 35 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 36 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 37 {0}, 38 }; 39 40 static const struct aipstz_cfg aipstz[] = { 41 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 44 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {0}, 46 }; 47 48 static const struct imx_rdc_cfg rdc[] = { 49 /* Master domain assignment */ 50 RDC_MDAn(RDC_MDA_M4, DID1), 51 52 /* peripherals domain permission */ 53 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 54 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 55 56 /* memory region */ 57 58 /* Sentinel */ 59 {0}, 60 }; 61 62 static const struct imx_csu_cfg csu_cfg[] = { 63 /* peripherals csl setting */ 64 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED), 65 66 /* master HP0~1 */ 67 68 /* SA setting */ 69 70 /* HP control setting */ 71 72 /* Sentinel */ 73 {0} 74 }; 75 76 static entry_point_info_t bl32_image_ep_info; 77 static entry_point_info_t bl33_image_ep_info; 78 79 /* get SPSR for BL33 entry */ 80 static uint32_t get_spsr_for_bl33_entry(void) 81 { 82 unsigned long el_status; 83 unsigned long mode; 84 uint32_t spsr; 85 86 /* figure out what mode we enter the non-secure world */ 87 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 88 el_status &= ID_AA64PFR0_ELX_MASK; 89 90 mode = (el_status) ? MODE_EL2 : MODE_EL1; 91 92 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 93 return spsr; 94 } 95 96 void bl31_tzc380_setup(void) 97 { 98 unsigned int val; 99 100 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 101 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 102 return; 103 104 tzc380_init(IMX_TZASC_BASE); 105 106 /* 107 * Need to substact offset 0x40000000 from CPU address when 108 * programming tzasc region for i.mx8mm. 109 */ 110 111 /* Enable 1G-5G S/NS RW */ 112 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 113 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 114 } 115 116 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 117 u_register_t arg2, u_register_t arg3) 118 { 119 static console_t console; 120 int i; 121 122 /* Enable CSU NS access permission */ 123 for (i = 0; i < 64; i++) { 124 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 125 } 126 127 imx_aipstz_init(aipstz); 128 129 imx_rdc_init(rdc); 130 131 imx_csu_init(csu_cfg); 132 133 imx8m_caam_init(); 134 135 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 136 IMX_CONSOLE_BAUDRATE, &console); 137 /* This console is only used for boot stage */ 138 console_set_scope(&console, CONSOLE_FLAG_BOOT); 139 140 /* 141 * tell BL3-1 where the non-secure software image is located 142 * and the entry state information. 143 */ 144 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 145 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 146 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 147 148 #if defined(SPD_opteed) || defined(SPD_trusty) 149 /* Populate entry point information for BL32 */ 150 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 151 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 152 bl32_image_ep_info.pc = BL32_BASE; 153 bl32_image_ep_info.spsr = 0; 154 155 #ifdef SPD_trusty 156 bl32_image_ep_info.args.arg0 = BL32_SIZE; 157 bl32_image_ep_info.args.arg1 = BL32_BASE; 158 #endif 159 /* Pass TEE base and size to bl33 */ 160 bl33_image_ep_info.args.arg1 = BL32_BASE; 161 bl33_image_ep_info.args.arg2 = BL32_SIZE; 162 #endif 163 164 bl31_tzc380_setup(); 165 } 166 167 void bl31_plat_arch_setup(void) 168 { 169 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 170 MT_MEMORY | MT_RW | MT_SECURE); 171 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 172 MT_MEMORY | MT_RO | MT_SECURE); 173 #if USE_COHERENT_MEM 174 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 175 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 176 MT_DEVICE | MT_RW | MT_SECURE); 177 #endif 178 /* Map TEE memory */ 179 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); 180 181 mmap_add(imx_mmap); 182 183 init_xlat_tables(); 184 185 enable_mmu_el3(0); 186 } 187 188 void bl31_platform_setup(void) 189 { 190 generic_delay_timer_init(); 191 192 /* select the CKIL source to 32K OSC */ 193 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 194 195 plat_gic_driver_init(); 196 plat_gic_init(); 197 198 imx_gpc_init(); 199 } 200 201 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 202 { 203 if (type == NON_SECURE) 204 return &bl33_image_ep_info; 205 if (type == SECURE) 206 return &bl32_image_ep_info; 207 208 return NULL; 209 } 210 211 unsigned int plat_get_syscnt_freq2(void) 212 { 213 return COUNTER_FREQUENCY; 214 } 215 216 #ifdef SPD_trusty 217 void plat_trusty_set_boot_args(aapcs64_params_t *args) 218 { 219 args->arg0 = BL32_SIZE; 220 args->arg1 = BL32_BASE; 221 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 222 } 223 #endif 224