1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_csu.h> 31 #include <plat_imx8.h> 32 33 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 34 35 static const mmap_region_t imx_mmap[] = { 36 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 37 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 38 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 39 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 40 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ 41 {0}, 42 }; 43 44 static const struct aipstz_cfg aipstz[] = { 45 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 49 {0}, 50 }; 51 52 static const struct imx_rdc_cfg rdc[] = { 53 /* Master domain assignment */ 54 RDC_MDAn(RDC_MDA_M4, DID1), 55 56 /* peripherals domain permission */ 57 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 58 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 59 60 /* memory region */ 61 62 /* Sentinel */ 63 {0}, 64 }; 65 66 static const struct imx_csu_cfg csu_cfg[] = { 67 /* peripherals csl setting */ 68 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED), 69 70 /* master HP0~1 */ 71 72 /* SA setting */ 73 74 /* HP control setting */ 75 76 /* Sentinel */ 77 {0} 78 }; 79 80 static entry_point_info_t bl32_image_ep_info; 81 static entry_point_info_t bl33_image_ep_info; 82 83 /* get SPSR for BL33 entry */ 84 static uint32_t get_spsr_for_bl33_entry(void) 85 { 86 unsigned long el_status; 87 unsigned long mode; 88 uint32_t spsr; 89 90 /* figure out what mode we enter the non-secure world */ 91 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 92 el_status &= ID_AA64PFR0_ELX_MASK; 93 94 mode = (el_status) ? MODE_EL2 : MODE_EL1; 95 96 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 97 return spsr; 98 } 99 100 void bl31_tzc380_setup(void) 101 { 102 unsigned int val; 103 104 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 105 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 106 return; 107 108 tzc380_init(IMX_TZASC_BASE); 109 110 /* 111 * Need to substact offset 0x40000000 from CPU address when 112 * programming tzasc region for i.mx8mm. 113 */ 114 115 /* Enable 1G-5G S/NS RW */ 116 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 117 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 118 } 119 120 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 121 u_register_t arg2, u_register_t arg3) 122 { 123 static console_t console; 124 int i; 125 126 /* Enable CSU NS access permission */ 127 for (i = 0; i < 64; i++) { 128 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 129 } 130 131 imx_aipstz_init(aipstz); 132 133 imx_rdc_init(rdc); 134 135 imx_csu_init(csu_cfg); 136 137 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 138 IMX_CONSOLE_BAUDRATE, &console); 139 /* This console is only used for boot stage */ 140 console_set_scope(&console, CONSOLE_FLAG_BOOT); 141 142 imx8m_caam_init(); 143 144 /* 145 * tell BL3-1 where the non-secure software image is located 146 * and the entry state information. 147 */ 148 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 149 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 150 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 151 152 #if defined(SPD_opteed) || defined(SPD_trusty) 153 /* Populate entry point information for BL32 */ 154 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 155 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 156 bl32_image_ep_info.pc = BL32_BASE; 157 bl32_image_ep_info.spsr = 0; 158 159 /* Pass TEE base and size to bl33 */ 160 bl33_image_ep_info.args.arg1 = BL32_BASE; 161 bl33_image_ep_info.args.arg2 = BL32_SIZE; 162 163 #ifdef SPD_trusty 164 bl32_image_ep_info.args.arg0 = BL32_SIZE; 165 bl32_image_ep_info.args.arg1 = BL32_BASE; 166 #else 167 /* Make sure memory is clean */ 168 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 169 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 170 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 171 #endif 172 #endif 173 174 bl31_tzc380_setup(); 175 } 176 177 void bl31_plat_arch_setup(void) 178 { 179 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 180 MT_MEMORY | MT_RW | MT_SECURE); 181 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 182 MT_MEMORY | MT_RO | MT_SECURE); 183 #if USE_COHERENT_MEM 184 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 185 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 186 MT_DEVICE | MT_RW | MT_SECURE); 187 #endif 188 /* Map TEE memory */ 189 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); 190 191 mmap_add(imx_mmap); 192 193 init_xlat_tables(); 194 195 enable_mmu_el3(0); 196 } 197 198 void bl31_platform_setup(void) 199 { 200 generic_delay_timer_init(); 201 202 /* select the CKIL source to 32K OSC */ 203 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 204 205 /* Init the dram info */ 206 dram_info_init(SAVED_DRAM_TIMING_BASE); 207 208 plat_gic_driver_init(); 209 plat_gic_init(); 210 211 imx_gpc_init(); 212 } 213 214 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 215 { 216 if (type == NON_SECURE) 217 return &bl33_image_ep_info; 218 if (type == SECURE) 219 return &bl32_image_ep_info; 220 221 return NULL; 222 } 223 224 unsigned int plat_get_syscnt_freq2(void) 225 { 226 return COUNTER_FREQUENCY; 227 } 228 229 #ifdef SPD_trusty 230 void plat_trusty_set_boot_args(aapcs64_params_t *args) 231 { 232 args->arg0 = BL32_SIZE; 233 args->arg1 = BL32_BASE; 234 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 235 } 236 #endif 237