1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_ccm.h> 31 #include <imx8m_csu.h> 32 #include <imx8m_snvs.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 /* 38 * Note: DRAM region is mapped with entire size available and uses MT_RW 39 * attributes. 40 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 41 * for explanation of this mapping scheme. 42 */ 43 static const mmap_region_t imx_mmap[] = { 44 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 45 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 46 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 47 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 48 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ 49 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */ 50 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */ 51 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */ 52 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */ 53 {0}, 54 }; 55 56 static const struct aipstz_cfg aipstz[] = { 57 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 58 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 59 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 60 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 61 {0}, 62 }; 63 64 static const struct imx_rdc_cfg rdc[] = { 65 /* Master domain assignment */ 66 RDC_MDAn(RDC_MDA_M4, DID1), 67 68 /* peripherals domain permission */ 69 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 70 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 71 72 /* memory region */ 73 74 /* Sentinel */ 75 {0}, 76 }; 77 78 static const struct imx_csu_cfg csu_cfg[] = { 79 /* peripherals csl setting */ 80 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED), 81 82 /* master HP0~1 */ 83 84 /* SA setting */ 85 86 /* HP control setting */ 87 88 /* Sentinel */ 89 {0} 90 }; 91 92 static entry_point_info_t bl32_image_ep_info; 93 static entry_point_info_t bl33_image_ep_info; 94 95 /* get SPSR for BL33 entry */ 96 static uint32_t get_spsr_for_bl33_entry(void) 97 { 98 unsigned long el_status; 99 unsigned long mode; 100 uint32_t spsr; 101 102 /* figure out what mode we enter the non-secure world */ 103 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 104 el_status &= ID_AA64PFR0_ELX_MASK; 105 106 mode = (el_status) ? MODE_EL2 : MODE_EL1; 107 108 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 109 return spsr; 110 } 111 112 void bl31_tzc380_setup(void) 113 { 114 unsigned int val; 115 116 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 117 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 118 return; 119 120 tzc380_init(IMX_TZASC_BASE); 121 122 /* 123 * Need to substact offset 0x40000000 from CPU address when 124 * programming tzasc region for i.mx8mm. 125 */ 126 127 /* Enable 1G-5G S/NS RW */ 128 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 129 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 130 } 131 132 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 133 u_register_t arg2, u_register_t arg3) 134 { 135 unsigned int console_base = IMX_BOOT_UART_BASE; 136 static console_t console; 137 int i; 138 139 /* Enable CSU NS access permission */ 140 for (i = 0; i < 64; i++) { 141 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 142 } 143 144 imx_aipstz_init(aipstz); 145 146 imx_rdc_init(rdc); 147 148 imx_csu_init(csu_cfg); 149 150 if (console_base == 0U) { 151 console_base = imx8m_uart_get_base(); 152 } 153 154 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 155 IMX_CONSOLE_BAUDRATE, &console); 156 /* This console is only used for boot stage */ 157 console_set_scope(&console, CONSOLE_FLAG_BOOT); 158 159 imx8m_caam_init(); 160 161 /* 162 * tell BL3-1 where the non-secure software image is located 163 * and the entry state information. 164 */ 165 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 166 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 167 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 168 169 #if defined(SPD_opteed) || defined(SPD_trusty) 170 /* Populate entry point information for BL32 */ 171 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 172 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 173 bl32_image_ep_info.pc = BL32_BASE; 174 bl32_image_ep_info.spsr = 0; 175 176 /* Pass TEE base and size to bl33 */ 177 bl33_image_ep_info.args.arg1 = BL32_BASE; 178 bl33_image_ep_info.args.arg2 = BL32_SIZE; 179 180 #ifdef SPD_trusty 181 bl32_image_ep_info.args.arg0 = BL32_SIZE; 182 bl32_image_ep_info.args.arg1 = BL32_BASE; 183 #else 184 /* Make sure memory is clean */ 185 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 186 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 187 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 188 #endif 189 #endif 190 191 #if !defined(SPD_opteed) && !defined(SPD_trusty) 192 enable_snvs_privileged_access(); 193 #endif 194 195 bl31_tzc380_setup(); 196 } 197 198 #define MAP_BL31_TOTAL \ 199 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 200 #define MAP_BL31_RO \ 201 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 202 #define MAP_COHERENT_MEM \ 203 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 204 MT_DEVICE | MT_RW | MT_SECURE) 205 #define MAP_BL32_TOTAL \ 206 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 207 208 void bl31_plat_arch_setup(void) 209 { 210 const mmap_region_t bl_regions[] = { 211 MAP_BL31_TOTAL, 212 MAP_BL31_RO, 213 #if USE_COHERENT_MEM 214 MAP_COHERENT_MEM, 215 #endif 216 #if defined(SPD_opteed) || defined(SPD_trusty) 217 /* Map TEE memory */ 218 MAP_BL32_TOTAL, 219 #endif 220 {0} 221 }; 222 223 setup_page_tables(bl_regions, imx_mmap); 224 enable_mmu_el3(0); 225 } 226 227 void bl31_platform_setup(void) 228 { 229 generic_delay_timer_init(); 230 231 /* select the CKIL source to 32K OSC */ 232 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 233 234 /* Init the dram info */ 235 dram_info_init(SAVED_DRAM_TIMING_BASE); 236 237 plat_gic_driver_init(); 238 plat_gic_init(); 239 240 imx_gpc_init(); 241 } 242 243 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 244 { 245 if (type == NON_SECURE) 246 return &bl33_image_ep_info; 247 if (type == SECURE) 248 return &bl32_image_ep_info; 249 250 return NULL; 251 } 252 253 unsigned int plat_get_syscnt_freq2(void) 254 { 255 return COUNTER_FREQUENCY; 256 } 257 258 #ifdef SPD_trusty 259 void plat_trusty_set_boot_args(aapcs64_params_t *args) 260 { 261 args->arg0 = BL32_SIZE; 262 args->arg1 = BL32_BASE; 263 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 264 } 265 #endif 266