1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_csu.h> 31 #include <plat_imx8.h> 32 33 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 34 35 static const mmap_region_t imx_mmap[] = { 36 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 37 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 38 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 39 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 40 {0}, 41 }; 42 43 static const struct aipstz_cfg aipstz[] = { 44 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {0}, 49 }; 50 51 static const struct imx_rdc_cfg rdc[] = { 52 /* Master domain assignment */ 53 RDC_MDAn(RDC_MDA_M4, DID1), 54 55 /* peripherals domain permission */ 56 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 57 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 58 59 /* memory region */ 60 61 /* Sentinel */ 62 {0}, 63 }; 64 65 static const struct imx_csu_cfg csu_cfg[] = { 66 /* peripherals csl setting */ 67 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED), 68 69 /* master HP0~1 */ 70 71 /* SA setting */ 72 73 /* HP control setting */ 74 75 /* Sentinel */ 76 {0} 77 }; 78 79 static entry_point_info_t bl32_image_ep_info; 80 static entry_point_info_t bl33_image_ep_info; 81 82 /* get SPSR for BL33 entry */ 83 static uint32_t get_spsr_for_bl33_entry(void) 84 { 85 unsigned long el_status; 86 unsigned long mode; 87 uint32_t spsr; 88 89 /* figure out what mode we enter the non-secure world */ 90 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 91 el_status &= ID_AA64PFR0_ELX_MASK; 92 93 mode = (el_status) ? MODE_EL2 : MODE_EL1; 94 95 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 96 return spsr; 97 } 98 99 void bl31_tzc380_setup(void) 100 { 101 unsigned int val; 102 103 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 104 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 105 return; 106 107 tzc380_init(IMX_TZASC_BASE); 108 109 /* 110 * Need to substact offset 0x40000000 from CPU address when 111 * programming tzasc region for i.mx8mm. 112 */ 113 114 /* Enable 1G-5G S/NS RW */ 115 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 116 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 117 } 118 119 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 120 u_register_t arg2, u_register_t arg3) 121 { 122 static console_t console; 123 int i; 124 125 /* Enable CSU NS access permission */ 126 for (i = 0; i < 64; i++) { 127 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 128 } 129 130 imx_aipstz_init(aipstz); 131 132 imx_rdc_init(rdc); 133 134 imx_csu_init(csu_cfg); 135 136 imx8m_caam_init(); 137 138 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 139 IMX_CONSOLE_BAUDRATE, &console); 140 /* This console is only used for boot stage */ 141 console_set_scope(&console, CONSOLE_FLAG_BOOT); 142 143 /* 144 * tell BL3-1 where the non-secure software image is located 145 * and the entry state information. 146 */ 147 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 148 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 149 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 150 151 #if defined(SPD_opteed) || defined(SPD_trusty) 152 /* Populate entry point information for BL32 */ 153 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 154 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 155 bl32_image_ep_info.pc = BL32_BASE; 156 bl32_image_ep_info.spsr = 0; 157 158 /* Pass TEE base and size to bl33 */ 159 bl33_image_ep_info.args.arg1 = BL32_BASE; 160 bl33_image_ep_info.args.arg2 = BL32_SIZE; 161 162 #ifdef SPD_trusty 163 bl32_image_ep_info.args.arg0 = BL32_SIZE; 164 bl32_image_ep_info.args.arg1 = BL32_BASE; 165 #else 166 /* Make sure memory is clean */ 167 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 168 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 169 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 170 #endif 171 #endif 172 173 bl31_tzc380_setup(); 174 } 175 176 void bl31_plat_arch_setup(void) 177 { 178 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 179 MT_MEMORY | MT_RW | MT_SECURE); 180 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 181 MT_MEMORY | MT_RO | MT_SECURE); 182 #if USE_COHERENT_MEM 183 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 184 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 185 MT_DEVICE | MT_RW | MT_SECURE); 186 #endif 187 /* Map TEE memory */ 188 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); 189 190 mmap_add(imx_mmap); 191 192 init_xlat_tables(); 193 194 enable_mmu_el3(0); 195 } 196 197 void bl31_platform_setup(void) 198 { 199 generic_delay_timer_init(); 200 201 /* select the CKIL source to 32K OSC */ 202 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 203 204 /* Init the dram info */ 205 dram_info_init(SAVED_DRAM_TIMING_BASE); 206 207 plat_gic_driver_init(); 208 plat_gic_init(); 209 210 imx_gpc_init(); 211 } 212 213 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 214 { 215 if (type == NON_SECURE) 216 return &bl33_image_ep_info; 217 if (type == SECURE) 218 return &bl32_image_ep_info; 219 220 return NULL; 221 } 222 223 unsigned int plat_get_syscnt_freq2(void) 224 { 225 return COUNTER_FREQUENCY; 226 } 227 228 #ifdef SPD_trusty 229 void plat_trusty_set_boot_args(aapcs64_params_t *args) 230 { 231 args->arg0 = BL32_SIZE; 232 args->arg1 = BL32_BASE; 233 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 234 } 235 #endif 236