1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_ccm.h> 31 #include <imx8m_csu.h> 32 #include <imx8m_snvs.h> 33 #include <plat_common.h> 34 #include <plat_imx8.h> 35 36 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 37 38 /* 39 * Note: DRAM region is mapped with entire size available and uses MT_RW 40 * attributes. 41 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 42 * for explanation of this mapping scheme. 43 */ 44 static const mmap_region_t imx_mmap[] = { 45 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 46 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 47 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 48 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 49 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ 50 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */ 51 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */ 52 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */ 53 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */ 54 {0}, 55 }; 56 57 static const struct aipstz_cfg aipstz[] = { 58 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 59 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 60 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 61 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 62 {0}, 63 }; 64 65 static struct imx_rdc_cfg rdc[] = { 66 /* Master domain assignment */ 67 RDC_MDAn(RDC_MDA_M4, DID1), 68 69 /* peripherals domain permission */ 70 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 71 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 72 73 /* memory region */ 74 75 /* Sentinel */ 76 {0}, 77 }; 78 79 static const struct imx_csu_cfg csu_cfg[] = { 80 /* peripherals csl setting */ 81 CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED), 82 CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED), 83 CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED), 84 85 /* master HP0~1 */ 86 87 /* SA setting */ 88 CSU_SA(CSU_SA_M4, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_VPU, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_GPU, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_APBHDMA, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_ENET, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 102 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 103 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 104 CSU_SA(CSU_SA_LCDIF, NON_SEC_ACCESS, LOCKED), 105 CSU_SA(CSU_SA_CSI, NON_SEC_ACCESS, LOCKED), 106 107 /* HP control setting */ 108 109 /* Sentinel */ 110 {0} 111 }; 112 113 static entry_point_info_t bl32_image_ep_info; 114 static entry_point_info_t bl33_image_ep_info; 115 116 /* get SPSR for BL33 entry */ 117 static uint32_t get_spsr_for_bl33_entry(void) 118 { 119 unsigned long el_status; 120 unsigned long mode; 121 uint32_t spsr; 122 123 /* figure out what mode we enter the non-secure world */ 124 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 125 el_status &= ID_AA64PFR0_ELX_MASK; 126 127 mode = (el_status) ? MODE_EL2 : MODE_EL1; 128 129 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 130 return spsr; 131 } 132 133 void bl31_tzc380_setup(void) 134 { 135 unsigned int val; 136 137 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 138 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 139 return; 140 141 tzc380_init(IMX_TZASC_BASE); 142 143 /* 144 * Need to substact offset 0x40000000 from CPU address when 145 * programming tzasc region for i.mx8mm. 146 */ 147 148 /* Enable 1G-5G S/NS RW */ 149 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 150 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 151 } 152 153 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 154 u_register_t arg2, u_register_t arg3) 155 { 156 unsigned int console_base = IMX_BOOT_UART_BASE; 157 static console_t console; 158 int i, ret; 159 160 /* Enable CSU NS access permission */ 161 for (i = 0; i < 64; i++) { 162 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 163 } 164 165 imx_aipstz_init(aipstz); 166 167 if (console_base == 0U) { 168 console_base = imx8m_uart_get_base(); 169 } 170 171 imx_rdc_init(rdc, console_base); 172 173 imx_csu_init(csu_cfg); 174 175 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 176 IMX_CONSOLE_BAUDRATE, &console); 177 /* This console is only used for boot stage */ 178 console_set_scope(&console, CONSOLE_FLAG_BOOT); 179 180 imx8m_caam_init(); 181 182 /* 183 * tell BL3-1 where the non-secure software image is located 184 * and the entry state information. 185 */ 186 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 187 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 188 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 189 190 #if defined(SPD_opteed) || defined(SPD_trusty) 191 /* Populate entry point information for BL32 */ 192 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 193 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 194 bl32_image_ep_info.pc = BL32_BASE; 195 bl32_image_ep_info.spsr = 0; 196 197 /* Pass TEE base and size to bl33 */ 198 bl33_image_ep_info.args.arg1 = BL32_BASE; 199 bl33_image_ep_info.args.arg2 = BL32_SIZE; 200 201 #ifdef SPD_trusty 202 bl32_image_ep_info.args.arg0 = BL32_SIZE; 203 bl32_image_ep_info.args.arg1 = BL32_BASE; 204 #else 205 /* Make sure memory is clean */ 206 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 207 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 208 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 209 #endif 210 #endif 211 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, 212 &bl32_image_ep_info, &bl33_image_ep_info); 213 if (ret != 0) { 214 ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, 215 &bl32_image_ep_info, 216 &bl33_image_ep_info); 217 } 218 219 #if !defined(SPD_opteed) && !defined(SPD_trusty) 220 enable_snvs_privileged_access(); 221 #endif 222 223 bl31_tzc380_setup(); 224 } 225 226 #define MAP_BL31_TOTAL \ 227 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 228 #define MAP_BL31_RO \ 229 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 230 #define MAP_COHERENT_MEM \ 231 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 232 MT_DEVICE | MT_RW | MT_SECURE) 233 #define MAP_BL32_TOTAL \ 234 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 235 236 void bl31_plat_arch_setup(void) 237 { 238 const mmap_region_t bl_regions[] = { 239 MAP_BL31_TOTAL, 240 MAP_BL31_RO, 241 #if USE_COHERENT_MEM 242 MAP_COHERENT_MEM, 243 #endif 244 #if defined(SPD_opteed) || defined(SPD_trusty) 245 /* Map TEE memory */ 246 MAP_BL32_TOTAL, 247 #endif 248 {0} 249 }; 250 251 setup_page_tables(bl_regions, imx_mmap); 252 enable_mmu_el3(0); 253 } 254 255 void bl31_platform_setup(void) 256 { 257 generic_delay_timer_init(); 258 259 /* select the CKIL source to 32K OSC */ 260 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 261 262 /* Init the dram info */ 263 dram_info_init(SAVED_DRAM_TIMING_BASE); 264 265 plat_gic_driver_init(); 266 plat_gic_init(); 267 268 imx_gpc_init(); 269 } 270 271 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 272 { 273 if (type == NON_SECURE) 274 return &bl33_image_ep_info; 275 if (type == SECURE) 276 return &bl32_image_ep_info; 277 278 return NULL; 279 } 280 281 unsigned int plat_get_syscnt_freq2(void) 282 { 283 return COUNTER_FREQUENCY; 284 } 285 286 #ifdef SPD_trusty 287 void plat_trusty_set_boot_args(aapcs64_params_t *args) 288 { 289 args->arg0 = BL32_SIZE; 290 args->arg1 = BL32_BASE; 291 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 292 } 293 #endif 294