1 /* 2 * Copyright 2019-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <bl31/interrupt_mgmt.h> 8 #include <common/runtime_svc.h> 9 #include <lib/mmio.h> 10 #include <lib/spinlock.h> 11 #include <plat/common/platform.h> 12 13 #include <dram.h> 14 15 #define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT 0x10 16 #define IMX_SIP_DDR_DVFS_GET_FREQ_INFO 0x11 17 18 struct dram_info dram_info; 19 20 /* lock used for DDR DVFS */ 21 spinlock_t dfs_lock; 22 23 static volatile uint32_t wfe_done; 24 static volatile bool wait_ddrc_hwffc_done = true; 25 static unsigned int dev_fsp = 0x1; 26 27 static uint32_t fsp_init_reg[3][4] = { 28 { DDRC_INIT3(0), DDRC_INIT4(0), DDRC_INIT6(0), DDRC_INIT7(0) }, 29 { DDRC_FREQ1_INIT3(0), DDRC_FREQ1_INIT4(0), DDRC_FREQ1_INIT6(0), DDRC_FREQ1_INIT7(0) }, 30 { DDRC_FREQ2_INIT3(0), DDRC_FREQ2_INIT4(0), DDRC_FREQ2_INIT6(0), DDRC_FREQ2_INIT7(0) }, 31 }; 32 33 static void get_mr_values(uint32_t (*mr_value)[8]) 34 { 35 uint32_t init_val; 36 unsigned int i, fsp_index; 37 38 for (fsp_index = 0U; fsp_index < 3U; fsp_index++) { 39 for (i = 0U; i < 4U; i++) { 40 init_val = mmio_read_32(fsp_init_reg[fsp_index][i]); 41 mr_value[fsp_index][2*i] = init_val >> 16; 42 mr_value[fsp_index][2*i + 1] = init_val & 0xFFFF; 43 } 44 } 45 } 46 47 static void save_rank_setting(void) 48 { 49 uint32_t i, offset; 50 uint32_t pstate_num = dram_info.num_fsp; 51 52 for (i = 0U; i < pstate_num; i++) { 53 offset = i ? (i + 1) * 0x1000 : 0U; 54 dram_info.rank_setting[i][0] = mmio_read_32(DDRC_DRAMTMG2(0) + offset); 55 if (dram_info.dram_type != DDRC_LPDDR4) { 56 dram_info.rank_setting[i][1] = mmio_read_32(DDRC_DRAMTMG9(0) + offset); 57 } 58 #if !defined(PLAT_imx8mq) 59 dram_info.rank_setting[i][2] = mmio_read_32(DDRC_RANKCTL(0) + offset); 60 #endif 61 } 62 #if defined(PLAT_imx8mq) 63 dram_info.rank_setting[0][2] = mmio_read_32(DDRC_RANKCTL(0)); 64 #endif 65 } 66 /* Restore the ddrc configs */ 67 void dram_umctl2_init(struct dram_timing_info *timing) 68 { 69 struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; 70 unsigned int i; 71 72 for (i = 0U; i < timing->ddrc_cfg_num; i++) { 73 mmio_write_32(ddrc_cfg->reg, ddrc_cfg->val); 74 ddrc_cfg++; 75 } 76 77 /* set the default fsp to P0 */ 78 mmio_write_32(DDRC_MSTR2(0), 0x0); 79 } 80 81 /* Restore the dram PHY config */ 82 void dram_phy_init(struct dram_timing_info *timing) 83 { 84 struct dram_cfg_param *cfg = timing->ddrphy_cfg; 85 unsigned int i; 86 87 /* Restore the PHY init config */ 88 cfg = timing->ddrphy_cfg; 89 for (i = 0U; i < timing->ddrphy_cfg_num; i++) { 90 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 91 cfg++; 92 } 93 94 /* Restore the DDR PHY CSRs */ 95 cfg = timing->ddrphy_trained_csr; 96 for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) { 97 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 98 cfg++; 99 } 100 101 /* Load the PIE image */ 102 cfg = timing->ddrphy_pie; 103 for (i = 0U; i < timing->ddrphy_pie_num; i++) { 104 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 105 cfg++; 106 } 107 } 108 109 /* EL3 SGI-8 IPI handler for DDR Dynamic frequency scaling */ 110 static uint64_t waiting_dvfs(uint32_t id, uint32_t flags, 111 void *handle, void *cookie) 112 { 113 uint64_t mpidr = read_mpidr_el1(); 114 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 115 uint32_t irq; 116 117 irq = plat_ic_acknowledge_interrupt(); 118 if (irq < 1022U) { 119 plat_ic_end_of_interrupt(irq); 120 } 121 122 /* set the WFE done status */ 123 spin_lock(&dfs_lock); 124 wfe_done |= (1 << cpu_id * 8); 125 dsb(); 126 spin_unlock(&dfs_lock); 127 128 while (1) { 129 /* ddr frequency change done */ 130 if (!wait_ddrc_hwffc_done) 131 break; 132 133 wfe(); 134 } 135 136 return 0; 137 } 138 139 void dram_info_init(unsigned long dram_timing_base) 140 { 141 uint32_t ddrc_mstr, current_fsp; 142 unsigned int idx = 0; 143 uint32_t flags = 0; 144 uint32_t rc; 145 unsigned int i; 146 147 /* Get the dram type & rank */ 148 ddrc_mstr = mmio_read_32(DDRC_MSTR(0)); 149 150 dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK; 151 dram_info.num_rank = ((ddrc_mstr >> 24) & ACTIVE_RANK_MASK) == 0x3 ? 152 DDRC_ACTIVE_TWO_RANK : DDRC_ACTIVE_ONE_RANK; 153 154 /* Get current fsp info */ 155 current_fsp = mmio_read_32(DDRC_DFIMISC(0)); 156 current_fsp = (current_fsp >> 8) & 0xf; 157 dram_info.boot_fsp = current_fsp; 158 dram_info.current_fsp = current_fsp; 159 160 get_mr_values(dram_info.mr_table); 161 162 dram_info.timing_info = (struct dram_timing_info *)dram_timing_base; 163 164 /* get the num of supported fsp */ 165 for (i = 0U; i < 4U; ++i) { 166 if (!dram_info.timing_info->fsp_table[i]) { 167 break; 168 } 169 idx = i; 170 } 171 dram_info.num_fsp = i; 172 173 /* save the DRAMTMG2/9 for rank to rank workaround */ 174 save_rank_setting(); 175 176 /* check if has bypass mode support */ 177 if (dram_info.timing_info->fsp_table[idx] < 666) { 178 dram_info.bypass_mode = true; 179 } else { 180 dram_info.bypass_mode = false; 181 } 182 183 /* Register the EL3 handler for DDR DVFS */ 184 set_interrupt_rm_flag(flags, NON_SECURE); 185 rc = register_interrupt_type_handler(INTR_TYPE_EL3, waiting_dvfs, flags); 186 if (rc != 0) { 187 panic(); 188 } 189 190 if (dram_info.dram_type == DDRC_LPDDR4 && current_fsp != 0x0) { 191 /* flush the L1/L2 cache */ 192 dcsw_op_all(DCCSW); 193 lpddr4_swffc(&dram_info, dev_fsp, 0x0); 194 dev_fsp = (~dev_fsp) & 0x1; 195 } else if (current_fsp != 0x0) { 196 /* flush the L1/L2 cache */ 197 dcsw_op_all(DCCSW); 198 ddr4_swffc(&dram_info, 0x0); 199 } 200 } 201 202 /* 203 * For each freq return the following info: 204 * 205 * r1: data rate 206 * r2: 1 + dram_core parent 207 * r3: 1 + dram_alt parent index 208 * r4: 1 + dram_apb parent index 209 * 210 * The parent indices can be used by an OS who manages source clocks to enabled 211 * them ahead of the switch. 212 * 213 * A parent value of "0" means "don't care". 214 * 215 * Current implementation of freq switch is hardcoded in 216 * plat/imx/common/imx8m/clock.c but in theory this can be enhanced to support 217 * a wide variety of rates. 218 */ 219 int dram_dvfs_get_freq_info(void *handle, u_register_t index) 220 { 221 switch (index) { 222 case 0: 223 SMC_RET4(handle, dram_info.timing_info->fsp_table[0], 224 1, 0, 5); 225 case 1: 226 if (!dram_info.bypass_mode) { 227 SMC_RET4(handle, dram_info.timing_info->fsp_table[1], 228 1, 0, 0); 229 } 230 SMC_RET4(handle, dram_info.timing_info->fsp_table[1], 231 2, 2, 4); 232 case 2: 233 if (!dram_info.bypass_mode) { 234 SMC_RET4(handle, dram_info.timing_info->fsp_table[2], 235 1, 0, 0); 236 } 237 SMC_RET4(handle, dram_info.timing_info->fsp_table[2], 238 2, 3, 3); 239 case 3: 240 SMC_RET4(handle, dram_info.timing_info->fsp_table[3], 241 1, 0, 0); 242 default: 243 SMC_RET1(handle, -3); 244 } 245 } 246 247 int dram_dvfs_handler(uint32_t smc_fid, void *handle, 248 u_register_t x1, u_register_t x2, u_register_t x3) 249 { 250 uint64_t mpidr = read_mpidr_el1(); 251 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 252 unsigned int fsp_index = x1; 253 uint32_t online_cores = x2; 254 255 if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_COUNT) { 256 SMC_RET1(handle, dram_info.num_fsp); 257 } else if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_INFO) { 258 return dram_dvfs_get_freq_info(handle, x2); 259 } else if (x1 < 4) { 260 wait_ddrc_hwffc_done = true; 261 dsb(); 262 263 /* trigger the SGI IPI to info other cores */ 264 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) { 265 if (cpu_id != i && (online_cores & (0x1 << (i * 8)))) { 266 plat_ic_raise_el3_sgi(0x8, i); 267 } 268 } 269 270 /* make sure all the core in WFE */ 271 online_cores &= ~(0x1 << (cpu_id * 8)); 272 while (1) { 273 if (online_cores == wfe_done) { 274 break; 275 } 276 } 277 278 /* flush the L1/L2 cache */ 279 dcsw_op_all(DCCSW); 280 281 if (dram_info.dram_type == DDRC_LPDDR4) { 282 lpddr4_swffc(&dram_info, dev_fsp, fsp_index); 283 dev_fsp = (~dev_fsp) & 0x1; 284 } else { 285 ddr4_swffc(&dram_info, fsp_index); 286 } 287 288 dram_info.current_fsp = fsp_index; 289 wait_ddrc_hwffc_done = false; 290 wfe_done = 0; 291 dsb(); 292 sev(); 293 isb(); 294 } 295 296 SMC_RET1(handle, 0); 297 } 298