1*c71793c6SJacky Bai /* 2*c71793c6SJacky Bai * Copyright 2019-2022 NXP 3*c71793c6SJacky Bai * 4*c71793c6SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*c71793c6SJacky Bai */ 6*c71793c6SJacky Bai 7*c71793c6SJacky Bai #include <lib/mmio.h> 8*c71793c6SJacky Bai 9*c71793c6SJacky Bai #include <dram.h> 10*c71793c6SJacky Bai 11*c71793c6SJacky Bai struct dram_info dram_info; 12*c71793c6SJacky Bai 13*c71793c6SJacky Bai /* Restore the ddrc configs */ 14*c71793c6SJacky Bai void dram_umctl2_init(struct dram_timing_info *timing) 15*c71793c6SJacky Bai { 16*c71793c6SJacky Bai struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; 17*c71793c6SJacky Bai unsigned int i; 18*c71793c6SJacky Bai 19*c71793c6SJacky Bai for (i = 0U; i < timing->ddrc_cfg_num; i++) { 20*c71793c6SJacky Bai mmio_write_32(ddrc_cfg->reg, ddrc_cfg->val); 21*c71793c6SJacky Bai ddrc_cfg++; 22*c71793c6SJacky Bai } 23*c71793c6SJacky Bai 24*c71793c6SJacky Bai /* set the default fsp to P0 */ 25*c71793c6SJacky Bai mmio_write_32(DDRC_MSTR2(0), 0x0); 26*c71793c6SJacky Bai } 27*c71793c6SJacky Bai 28*c71793c6SJacky Bai /* Restore the dram PHY config */ 29*c71793c6SJacky Bai void dram_phy_init(struct dram_timing_info *timing) 30*c71793c6SJacky Bai { 31*c71793c6SJacky Bai struct dram_cfg_param *cfg = timing->ddrphy_cfg; 32*c71793c6SJacky Bai unsigned int i; 33*c71793c6SJacky Bai 34*c71793c6SJacky Bai /* Restore the PHY init config */ 35*c71793c6SJacky Bai cfg = timing->ddrphy_cfg; 36*c71793c6SJacky Bai for (i = 0U; i < timing->ddrphy_cfg_num; i++) { 37*c71793c6SJacky Bai dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 38*c71793c6SJacky Bai cfg++; 39*c71793c6SJacky Bai } 40*c71793c6SJacky Bai 41*c71793c6SJacky Bai /* Restore the DDR PHY CSRs */ 42*c71793c6SJacky Bai cfg = timing->ddrphy_trained_csr; 43*c71793c6SJacky Bai for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) { 44*c71793c6SJacky Bai dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 45*c71793c6SJacky Bai cfg++; 46*c71793c6SJacky Bai } 47*c71793c6SJacky Bai 48*c71793c6SJacky Bai /* Load the PIE image */ 49*c71793c6SJacky Bai cfg = timing->ddrphy_pie; 50*c71793c6SJacky Bai for (i = 0U; i < timing->ddrphy_pie_num; i++) { 51*c71793c6SJacky Bai dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 52*c71793c6SJacky Bai cfg++; 53*c71793c6SJacky Bai } 54*c71793c6SJacky Bai } 55*c71793c6SJacky Bai 56*c71793c6SJacky Bai void dram_info_init(unsigned long dram_timing_base) 57*c71793c6SJacky Bai { 58*c71793c6SJacky Bai uint32_t ddrc_mstr, current_fsp; 59*c71793c6SJacky Bai 60*c71793c6SJacky Bai /* Get the dram type & rank */ 61*c71793c6SJacky Bai ddrc_mstr = mmio_read_32(DDRC_MSTR(0)); 62*c71793c6SJacky Bai 63*c71793c6SJacky Bai dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK; 64*c71793c6SJacky Bai dram_info.num_rank = (ddrc_mstr >> 24) & ACTIVE_RANK_MASK; 65*c71793c6SJacky Bai 66*c71793c6SJacky Bai /* Get current fsp info */ 67*c71793c6SJacky Bai current_fsp = mmio_read_32(DDRC_DFIMISC(0)) & 0xf; 68*c71793c6SJacky Bai dram_info.boot_fsp = current_fsp; 69*c71793c6SJacky Bai dram_info.current_fsp = current_fsp; 70*c71793c6SJacky Bai 71*c71793c6SJacky Bai dram_info.timing_info = (struct dram_timing_info *)dram_timing_base; 72*c71793c6SJacky Bai } 73