1ff2743e5SAnson Huang /* 2ff2743e5SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3ff2743e5SAnson Huang * 4ff2743e5SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5ff2743e5SAnson Huang */ 6ff2743e5SAnson Huang 793c78ed2SAntonio Nino Diaz #include <stdint.h> 8ff2743e5SAnson Huang 9ff2743e5SAnson Huang #define MU_ATR0_OFFSET1 0x0 10ff2743e5SAnson Huang #define MU_ARR0_OFFSET1 0x10 11ff2743e5SAnson Huang #define MU_ASR_OFFSET1 0x20 12ff2743e5SAnson Huang #define MU_ACR_OFFSET1 0x24 13ff2743e5SAnson Huang #define MU_TR_COUNT1 4 14ff2743e5SAnson Huang #define MU_RR_COUNT1 4 15ff2743e5SAnson Huang 16*dc5baeb3SJustin Chadwell #define MU_CR_GIEn_MASK1 (0xFu << 28) 17ff2743e5SAnson Huang #define MU_CR_RIEn_MASK1 (0xF << 24) 18ff2743e5SAnson Huang #define MU_CR_TIEn_MASK1 (0xF << 20) 19ff2743e5SAnson Huang #define MU_CR_GIRn_MASK1 (0xF << 16) 20ff2743e5SAnson Huang #define MU_CR_NMI_MASK1 (1 << 3) 21ff2743e5SAnson Huang #define MU_CR_Fn_MASK1 0x7 22ff2743e5SAnson Huang 23ff2743e5SAnson Huang #define MU_SR_TE0_MASK1 (1 << 23) 24ff2743e5SAnson Huang #define MU_SR_RF0_MASK1 (1 << 27) 25ff2743e5SAnson Huang #define MU_CR_RIE0_MASK1 (1 << 27) 26*dc5baeb3SJustin Chadwell #define MU_CR_GIE0_MASK1 (1U << 31) 27ff2743e5SAnson Huang 28ff2743e5SAnson Huang #define MU_TR_COUNT 4 29ff2743e5SAnson Huang #define MU_RR_COUNT 4 30ff2743e5SAnson Huang 31ff2743e5SAnson Huang void MU_Init(uint32_t base); 32ff2743e5SAnson Huang void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg); 33ff2743e5SAnson Huang void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg); 34ff2743e5SAnson Huang void MU_EnableGeneralInt(uint32_t base, uint32_t index); 35ff2743e5SAnson Huang void MU_EnableRxFullInt(uint32_t base, uint32_t index); 363a2b5199SAnson Huang void MU_Resume(uint32_t base); 37