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d0d0f171 |
| 16-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jc/shift-overflow" into integration
* changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behavi
Merge changes from topic "jc/shift-overflow" into integration
* changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour
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| #
dc5baeb3 |
| 03-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Update imx platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit.
Change
Update imx platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit.
Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| #
44b935c0 |
| 30-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1789 from Anson-Huang/lpm
Add power optimization for i.MX8QM/i.MX8QX
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| #
3a2b5199 |
| 24-Jan-2019 |
Anson Huang <Anson.Huang@nxp.com> |
imx: power optimization for i.mx8qm
Current implementation of i.MX8QM power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kep
imx: power optimization for i.mx8qm
Current implementation of i.MX8QM power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug.
To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend.
If resources are powered off for suspend, they should be restored properly after system resume.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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6d4f6aea |
| 22-Aug-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1528 from antonio-nino-diaz-arm/an/libc
libc: Cleanup library
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93c78ed2 |
| 16-Aug-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
libc: Fix all includes in codebase
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers.
Change-Id: I530f71d9510cb03
libc: Fix all includes in codebase
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers.
Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| #
d135ad78 |
| 19-Jun-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1410 from Anson-Huang/master
Add NXP's i.MX8QX and i.MX8QM SoC support
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| #
ff2743e5 |
| 05-Jun-2018 |
Anson Huang <Anson.Huang@nxp.com> |
Support for NXP's i.MX8 SoCs IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of clock management, power management, partition management, PAD management etc., other cluster
Support for NXP's i.MX8 SoCs IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of clock management, power management, partition management, PAD management etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for clock/power management etc..
This patch adds basic IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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