1bd08def3SAnson Huang/* 2*fcd41e86SJacky Bai * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3bd08def3SAnson Huang * 4bd08def3SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5bd08def3SAnson Huang */ 6bd08def3SAnson Huang 7bd08def3SAnson Huang#include <asm_macros.S> 8bd08def3SAnson Huang#include <platform_def.h> 9bd08def3SAnson Huang#include <cortex_a35.h> 10bd08def3SAnson Huang 11bd08def3SAnson Huang .globl plat_is_my_cpu_primary 12bd08def3SAnson Huang .globl plat_my_core_pos 13bd08def3SAnson Huang .globl plat_calc_core_pos 14bd08def3SAnson Huang .globl plat_reset_handler 15bd08def3SAnson Huang .globl plat_get_my_entrypoint 16bd08def3SAnson Huang .globl plat_secondary_cold_boot_setup 17bd08def3SAnson Huang .globl plat_crash_console_init 18bd08def3SAnson Huang .globl plat_crash_console_putc 199c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 20bd08def3SAnson Huang .globl platform_mem_init 21bd08def3SAnson Huang .globl imx_mailbox_init 22bd08def3SAnson Huang 23bd08def3SAnson Huang /* -------------------------------------------------------------------- 24bd08def3SAnson Huang * Helper macro that reads the part number of the current CPU and jumps 25bd08def3SAnson Huang * to the given label if it matches the CPU MIDR provided. 26bd08def3SAnson Huang * 27bd08def3SAnson Huang * Clobbers x0. 28bd08def3SAnson Huang * -------------------------------------------------------------------- 29bd08def3SAnson Huang */ 30bd08def3SAnson Huang .macro jump_if_cpu_midr _cpu_midr, _label 31bd08def3SAnson Huang 32bd08def3SAnson Huang mrs x0, midr_el1 33bd08def3SAnson Huang ubfx x0, x0, MIDR_PN_SHIFT, #12 34bd08def3SAnson Huang cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 35bd08def3SAnson Huang b.eq \_label 36bd08def3SAnson Huang 37bd08def3SAnson Huang .endm 38bd08def3SAnson Huang 39bd08def3SAnson Huang /* ---------------------------------------------- 40bd08def3SAnson Huang * The mailbox_base is used to distinguish warm/cold 41bd08def3SAnson Huang * reset. The mailbox_base is in the data section, not 42bd08def3SAnson Huang * in .bss, this allows function to start using this 43bd08def3SAnson Huang * variable before the runtime memory is initialized. 44bd08def3SAnson Huang * ---------------------------------------------- 45bd08def3SAnson Huang */ 46bd08def3SAnson Huang .section .data.mailbox_base 47bd08def3SAnson Huang .align 3 48bd08def3SAnson Huang mailbox_base: .quad 0x0 49bd08def3SAnson Huang 50bd08def3SAnson Huang /* ---------------------------------------------- 51bd08def3SAnson Huang * unsigned int plat_is_my_cpu_primary(void); 52bd08def3SAnson Huang * This function checks if this is the primary CPU 53bd08def3SAnson Huang * ---------------------------------------------- 54bd08def3SAnson Huang */ 55bd08def3SAnson Huangfunc plat_is_my_cpu_primary 56bd08def3SAnson Huang mrs x0, mpidr_el1 57bd08def3SAnson Huang and x0, x0, #(MPIDR_CPU_MASK) 58bd08def3SAnson Huang cmp x0, #PLAT_PRIMARY_CPU 59bd08def3SAnson Huang cset x0, eq 60bd08def3SAnson Huang ret 61bd08def3SAnson Huangendfunc plat_is_my_cpu_primary 62bd08def3SAnson Huang 63bd08def3SAnson Huang /* ---------------------------------------------- 64bd08def3SAnson Huang * unsigned int plat_my_core_pos(void) 65bd08def3SAnson Huang * This Function uses the plat_calc_core_pos() 66bd08def3SAnson Huang * to get the index of the calling CPU. 67bd08def3SAnson Huang * ---------------------------------------------- 68bd08def3SAnson Huang */ 69bd08def3SAnson Huangfunc plat_my_core_pos 70bd08def3SAnson Huang mrs x0, mpidr_el1 71bd08def3SAnson Huang and x1, x0, #MPIDR_CPU_MASK 72bd08def3SAnson Huang and x0, x0, #MPIDR_CLUSTER_MASK 73bd08def3SAnson Huang add x0, x1, x0, LSR #6 74bd08def3SAnson Huang ret 75bd08def3SAnson Huangendfunc plat_my_core_pos 76bd08def3SAnson Huang 77bd08def3SAnson Huang /* 78bd08def3SAnson Huang * unsigned int plat_calc_core_pos(uint64_t mpidr) 79bd08def3SAnson Huang * helper function to calculate the core position. 80bd08def3SAnson Huang * With this function. 81bd08def3SAnson Huang */ 82bd08def3SAnson Huangfunc plat_calc_core_pos 83bd08def3SAnson Huang and x1, x0, #MPIDR_CPU_MASK 84bd08def3SAnson Huang and x0, x0, #MPIDR_CLUSTER_MASK 85bd08def3SAnson Huang add x0, x1, x0, LSR #6 86bd08def3SAnson Huang ret 87bd08def3SAnson Huangendfunc plat_calc_core_pos 88bd08def3SAnson Huang 89*fcd41e86SJacky Bai /* ---------------------------------------------- 90*fcd41e86SJacky Bai * function to handle platform specific reset. 91*fcd41e86SJacky Bai * ---------------------------------------------- 92*fcd41e86SJacky Bai */ 93*fcd41e86SJacky Baifunc plat_reset_handler 94*fcd41e86SJacky Bai#if defined(PLAT_imx8ulp) 95*fcd41e86SJacky Bai mrs x0, CORTEX_A35_CPUECTLR_EL1 96*fcd41e86SJacky Bai orr x0, x0, #(0x1 << 0) 97*fcd41e86SJacky Bai orr x0, x0, #(0x1 << 3) 98*fcd41e86SJacky Bai msr CORTEX_A35_CPUECTLR_EL1, x0 99*fcd41e86SJacky Bai 100*fcd41e86SJacky Bai mrs x0, CORTEX_A35_L2ECTLR_EL1 101*fcd41e86SJacky Bai orr x0, x0, #(0x1 << 0) 102*fcd41e86SJacky Bai msr CORTEX_A35_L2ECTLR_EL1, x0 103*fcd41e86SJacky Bai isb 104*fcd41e86SJacky Bai#endif 105*fcd41e86SJacky Bai /* enable EL2 cpuectlr RW access */ 106*fcd41e86SJacky Bai mov x0, #0x73 107*fcd41e86SJacky Bai msr actlr_el3, x0 108*fcd41e86SJacky Bai msr actlr_el2, x0 109*fcd41e86SJacky Bai isb 110*fcd41e86SJacky Bai 111*fcd41e86SJacky Bai ret 112*fcd41e86SJacky Baiendfunc plat_reset_handler 113*fcd41e86SJacky Bai 114bd08def3SAnson Huang /* --------------------------------------------- 115bd08def3SAnson Huang * function to get the entrypoint. 116bd08def3SAnson Huang * --------------------------------------------- 117bd08def3SAnson Huang */ 118bd08def3SAnson Huangfunc plat_get_my_entrypoint 119bd08def3SAnson Huang adrp x1, mailbox_base 120bd08def3SAnson Huang ldr x0, [x1, :lo12:mailbox_base] 121bd08def3SAnson Huang ret 122bd08def3SAnson Huangendfunc plat_get_my_entrypoint 123bd08def3SAnson Huang 124bd08def3SAnson Huangfunc imx_mailbox_init 125bd08def3SAnson Huang adrp x1, mailbox_base 126bd08def3SAnson Huang str x0, [x1, :lo12:mailbox_base] 127bd08def3SAnson Huang ret 128bd08def3SAnson Huangendfunc imx_mailbox_init 129bd08def3SAnson Huang 130bd08def3SAnson Huangfunc plat_secondary_cold_boot_setup 131bd08def3SAnson Huang b . 132bd08def3SAnson Huangendfunc plat_secondary_cold_boot_setup 133bd08def3SAnson Huang 134bd08def3SAnson Huangfunc plat_crash_console_init 1359c675b37SAntonio Nino Diaz mov x0, #1 136bd08def3SAnson Huang ret 137bd08def3SAnson Huangendfunc plat_crash_console_init 138bd08def3SAnson Huang 139bd08def3SAnson Huangfunc plat_crash_console_putc 140bd08def3SAnson Huang ret 141bd08def3SAnson Huangendfunc plat_crash_console_putc 142bd08def3SAnson Huang 1439c675b37SAntonio Nino Diazfunc plat_crash_console_flush 1449c675b37SAntonio Nino Diaz mov x0, #0 1459c675b37SAntonio Nino Diaz ret 1469c675b37SAntonio Nino Diazendfunc plat_crash_console_flush 1479c675b37SAntonio Nino Diaz 148bd08def3SAnson Huangfunc platform_mem_init 149bd08def3SAnson Huang ret 150bd08def3SAnson Huangendfunc platform_mem_init 151