1*bd08def3SAnson Huang/* 2*bd08def3SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*bd08def3SAnson Huang * 4*bd08def3SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5*bd08def3SAnson Huang */ 6*bd08def3SAnson Huang 7*bd08def3SAnson Huang#include <asm_macros.S> 8*bd08def3SAnson Huang#include <platform_def.h> 9*bd08def3SAnson Huang#include <cortex_a35.h> 10*bd08def3SAnson Huang 11*bd08def3SAnson Huang .globl plat_is_my_cpu_primary 12*bd08def3SAnson Huang .globl plat_my_core_pos 13*bd08def3SAnson Huang .globl plat_calc_core_pos 14*bd08def3SAnson Huang .globl plat_reset_handler 15*bd08def3SAnson Huang .globl plat_get_my_entrypoint 16*bd08def3SAnson Huang .globl plat_secondary_cold_boot_setup 17*bd08def3SAnson Huang .globl plat_crash_console_init 18*bd08def3SAnson Huang .globl plat_crash_console_putc 19*bd08def3SAnson Huang .globl platform_mem_init 20*bd08def3SAnson Huang .globl imx_mailbox_init 21*bd08def3SAnson Huang 22*bd08def3SAnson Huang /* -------------------------------------------------------------------- 23*bd08def3SAnson Huang * Helper macro that reads the part number of the current CPU and jumps 24*bd08def3SAnson Huang * to the given label if it matches the CPU MIDR provided. 25*bd08def3SAnson Huang * 26*bd08def3SAnson Huang * Clobbers x0. 27*bd08def3SAnson Huang * -------------------------------------------------------------------- 28*bd08def3SAnson Huang */ 29*bd08def3SAnson Huang .macro jump_if_cpu_midr _cpu_midr, _label 30*bd08def3SAnson Huang 31*bd08def3SAnson Huang mrs x0, midr_el1 32*bd08def3SAnson Huang ubfx x0, x0, MIDR_PN_SHIFT, #12 33*bd08def3SAnson Huang cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 34*bd08def3SAnson Huang b.eq \_label 35*bd08def3SAnson Huang 36*bd08def3SAnson Huang .endm 37*bd08def3SAnson Huang 38*bd08def3SAnson Huang /* ---------------------------------------------- 39*bd08def3SAnson Huang * The mailbox_base is used to distinguish warm/cold 40*bd08def3SAnson Huang * reset. The mailbox_base is in the data section, not 41*bd08def3SAnson Huang * in .bss, this allows function to start using this 42*bd08def3SAnson Huang * variable before the runtime memory is initialized. 43*bd08def3SAnson Huang * ---------------------------------------------- 44*bd08def3SAnson Huang */ 45*bd08def3SAnson Huang .section .data.mailbox_base 46*bd08def3SAnson Huang .align 3 47*bd08def3SAnson Huang mailbox_base: .quad 0x0 48*bd08def3SAnson Huang 49*bd08def3SAnson Huang /* ---------------------------------------------- 50*bd08def3SAnson Huang * unsigned int plat_is_my_cpu_primary(void); 51*bd08def3SAnson Huang * This function checks if this is the primary CPU 52*bd08def3SAnson Huang * ---------------------------------------------- 53*bd08def3SAnson Huang */ 54*bd08def3SAnson Huangfunc plat_is_my_cpu_primary 55*bd08def3SAnson Huang mrs x0, mpidr_el1 56*bd08def3SAnson Huang and x0, x0, #(MPIDR_CPU_MASK) 57*bd08def3SAnson Huang cmp x0, #PLAT_PRIMARY_CPU 58*bd08def3SAnson Huang cset x0, eq 59*bd08def3SAnson Huang ret 60*bd08def3SAnson Huangendfunc plat_is_my_cpu_primary 61*bd08def3SAnson Huang 62*bd08def3SAnson Huang /* ---------------------------------------------- 63*bd08def3SAnson Huang * unsigned int plat_my_core_pos(void) 64*bd08def3SAnson Huang * This Function uses the plat_calc_core_pos() 65*bd08def3SAnson Huang * to get the index of the calling CPU. 66*bd08def3SAnson Huang * ---------------------------------------------- 67*bd08def3SAnson Huang */ 68*bd08def3SAnson Huangfunc plat_my_core_pos 69*bd08def3SAnson Huang mrs x0, mpidr_el1 70*bd08def3SAnson Huang and x1, x0, #MPIDR_CPU_MASK 71*bd08def3SAnson Huang and x0, x0, #MPIDR_CLUSTER_MASK 72*bd08def3SAnson Huang add x0, x1, x0, LSR #6 73*bd08def3SAnson Huang ret 74*bd08def3SAnson Huangendfunc plat_my_core_pos 75*bd08def3SAnson Huang 76*bd08def3SAnson Huang /* 77*bd08def3SAnson Huang * unsigned int plat_calc_core_pos(uint64_t mpidr) 78*bd08def3SAnson Huang * helper function to calculate the core position. 79*bd08def3SAnson Huang * With this function. 80*bd08def3SAnson Huang */ 81*bd08def3SAnson Huangfunc plat_calc_core_pos 82*bd08def3SAnson Huang and x1, x0, #MPIDR_CPU_MASK 83*bd08def3SAnson Huang and x0, x0, #MPIDR_CLUSTER_MASK 84*bd08def3SAnson Huang add x0, x1, x0, LSR #6 85*bd08def3SAnson Huang ret 86*bd08def3SAnson Huangendfunc plat_calc_core_pos 87*bd08def3SAnson Huang 88*bd08def3SAnson Huang /* --------------------------------------------- 89*bd08def3SAnson Huang * function to get the entrypoint. 90*bd08def3SAnson Huang * --------------------------------------------- 91*bd08def3SAnson Huang */ 92*bd08def3SAnson Huangfunc plat_get_my_entrypoint 93*bd08def3SAnson Huang adrp x1, mailbox_base 94*bd08def3SAnson Huang ldr x0, [x1, :lo12:mailbox_base] 95*bd08def3SAnson Huang ret 96*bd08def3SAnson Huangendfunc plat_get_my_entrypoint 97*bd08def3SAnson Huang 98*bd08def3SAnson Huangfunc imx_mailbox_init 99*bd08def3SAnson Huang adrp x1, mailbox_base 100*bd08def3SAnson Huang str x0, [x1, :lo12:mailbox_base] 101*bd08def3SAnson Huang ret 102*bd08def3SAnson Huangendfunc imx_mailbox_init 103*bd08def3SAnson Huang 104*bd08def3SAnson Huangfunc plat_secondary_cold_boot_setup 105*bd08def3SAnson Huang b . 106*bd08def3SAnson Huangendfunc plat_secondary_cold_boot_setup 107*bd08def3SAnson Huang 108*bd08def3SAnson Huangfunc plat_crash_console_init 109*bd08def3SAnson Huang ret 110*bd08def3SAnson Huangendfunc plat_crash_console_init 111*bd08def3SAnson Huang 112*bd08def3SAnson Huangfunc plat_crash_console_putc 113*bd08def3SAnson Huang ret 114*bd08def3SAnson Huangendfunc plat_crash_console_putc 115*bd08def3SAnson Huang 116*bd08def3SAnson Huangfunc platform_mem_init 117*bd08def3SAnson Huang ret 118*bd08def3SAnson Huangendfunc platform_mem_init 119