1*85f199b7SChia-Wei Wang /* 2*85f199b7SChia-Wei Wang * Copyright (c) 2023, Aspeed Technology Inc. 3*85f199b7SChia-Wei Wang * 4*85f199b7SChia-Wei Wang * SPDX-License-Identifier: BSD-3-Clause 5*85f199b7SChia-Wei Wang */ 6*85f199b7SChia-Wei Wang 7*85f199b7SChia-Wei Wang #ifndef PLATFORM_DEF_H 8*85f199b7SChia-Wei Wang #define PLATFORM_DEF_H 9*85f199b7SChia-Wei Wang 10*85f199b7SChia-Wei Wang #include <arch.h> 11*85f199b7SChia-Wei Wang #include <plat/common/common_def.h> 12*85f199b7SChia-Wei Wang #include <platform_reg.h> 13*85f199b7SChia-Wei Wang 14*85f199b7SChia-Wei Wang #define PLATFORM_STACK_SIZE UL(0x1000) 15*85f199b7SChia-Wei Wang 16*85f199b7SChia-Wei Wang /* cpu topology */ 17*85f199b7SChia-Wei Wang #define PLATFORM_SYSTEM_COUNT U(1) 18*85f199b7SChia-Wei Wang #define PLATFORM_CLUSTER_COUNT U(1) 19*85f199b7SChia-Wei Wang #define PLATFORM_CORE_PRIMARY U(0) 20*85f199b7SChia-Wei Wang #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) 21*85f199b7SChia-Wei Wang #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 22*85f199b7SChia-Wei Wang PLATFORM_CORE_COUNT_PER_CLUSTER) 23*85f199b7SChia-Wei Wang 24*85f199b7SChia-Wei Wang /* arch timer */ 25*85f199b7SChia-Wei Wang #define PLAT_SYSCNT_CLKIN_HZ U(1600000000) 26*85f199b7SChia-Wei Wang 27*85f199b7SChia-Wei Wang /* power domain */ 28*85f199b7SChia-Wei Wang #define PLAT_MAX_PWR_LVL U(1) 29*85f199b7SChia-Wei Wang #define PLAT_NUM_PWR_DOMAINS U(5) 30*85f199b7SChia-Wei Wang #define PLAT_MAX_RET_STATE U(1) 31*85f199b7SChia-Wei Wang #define PLAT_MAX_OFF_STATE U(2) 32*85f199b7SChia-Wei Wang 33*85f199b7SChia-Wei Wang /* cache line size */ 34*85f199b7SChia-Wei Wang #define CACHE_WRITEBACK_SHIFT U(6) 35*85f199b7SChia-Wei Wang #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 36*85f199b7SChia-Wei Wang 37*85f199b7SChia-Wei Wang /* translation tables */ 38*85f199b7SChia-Wei Wang #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) 39*85f199b7SChia-Wei Wang #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 40*85f199b7SChia-Wei Wang #define MAX_XLAT_TABLES U(8) 41*85f199b7SChia-Wei Wang #define MAX_MMAP_REGIONS U(32) 42*85f199b7SChia-Wei Wang 43*85f199b7SChia-Wei Wang /* BL31 region */ 44*85f199b7SChia-Wei Wang #define BL31_BASE ULL(0x400000000) 45*85f199b7SChia-Wei Wang #define BL31_SIZE ULL(0x400000) 46*85f199b7SChia-Wei Wang #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 47*85f199b7SChia-Wei Wang 48*85f199b7SChia-Wei Wang /* BL32 region */ 49*85f199b7SChia-Wei Wang #define BL32_BASE BL31_LIMIT 50*85f199b7SChia-Wei Wang #define BL32_SIZE ULL(0x400000) 51*85f199b7SChia-Wei Wang #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 52*85f199b7SChia-Wei Wang 53*85f199b7SChia-Wei Wang /* console */ 54*85f199b7SChia-Wei Wang #define CONSOLE_UART_BASE UART12_BASE 55*85f199b7SChia-Wei Wang #define CONSOLE_UART_CLKIN_HZ U(1846153) 56*85f199b7SChia-Wei Wang #define CONSOLE_UART_BAUDRATE U(115200) 57*85f199b7SChia-Wei Wang 58*85f199b7SChia-Wei Wang #endif /* PLATFORM_DEF_H */ 59