1 /* 2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <bl31/interrupt_mgmt.h> 13 #include <common/debug.h> 14 #include <drivers/arm/css/css_scp.h> 15 #include <lib/cassert.h> 16 #include <plat/arm/common/plat_arm.h> 17 18 #include <plat/common/platform.h> 19 20 #include <plat/arm/css/common/css_pm.h> 21 22 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ 23 #pragma weak plat_arm_psci_pm_ops 24 25 #if ARM_RECOM_STATE_ID_ENC 26 /* 27 * The table storing the valid idle power states. Ensure that the 28 * array entries are populated in ascending order of state-id to 29 * enable us to use binary search during power state validation. 30 * The table must be terminated by a NULL entry. 31 */ 32 const unsigned int arm_pm_idle_states[] = { 33 /* State-id - 0x001 */ 34 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 35 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 36 /* State-id - 0x002 */ 37 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 38 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 39 /* State-id - 0x022 */ 40 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 41 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 42 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 43 /* State-id - 0x222 */ 44 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 45 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 46 #endif 47 0, 48 }; 49 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 50 51 /* 52 * All the power management helpers in this file assume at least cluster power 53 * level is supported. 54 */ 55 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, 56 assert_max_pwr_lvl_supported_mismatch); 57 58 /* 59 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL 60 * assumed by the CSS layer. 61 */ 62 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL, 63 assert_max_pwr_lvl_higher_than_css_sys_lvl); 64 65 /******************************************************************************* 66 * Handler called when a power domain is about to be turned on. The 67 * level and mpidr determine the affinity instance. 68 ******************************************************************************/ 69 int css_pwr_domain_on(u_register_t mpidr) 70 { 71 css_scp_on(mpidr); 72 73 return PSCI_E_SUCCESS; 74 } 75 76 static void css_pwr_domain_on_finisher_common( 77 const psci_power_state_t *target_state) 78 { 79 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 80 81 /* 82 * Perform the common cluster specific operations i.e enable coherency 83 * if this cluster was off. 84 */ 85 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 86 plat_arm_interconnect_enter_coherency(); 87 } 88 89 /******************************************************************************* 90 * Handler called when a power level has just been powered on after 91 * being turned off earlier. The target_state encodes the low power state that 92 * each level has woken up from. This handler would never be invoked with 93 * the system power domain uninitialized as either the primary would have taken 94 * care of it as part of cold boot or the first core awakened from system 95 * suspend would have already initialized it. 96 ******************************************************************************/ 97 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 98 { 99 /* Assert that the system power domain need not be initialized */ 100 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 101 102 css_pwr_domain_on_finisher_common(target_state); 103 } 104 105 /******************************************************************************* 106 * Handler called when a power domain has just been powered on and the cpu 107 * and its cluster are fully participating in coherent transaction on the 108 * interconnect. Data cache must be enabled for CPU at this point. 109 ******************************************************************************/ 110 void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) 111 { 112 /* Program the gic per-cpu distributor or re-distributor interface */ 113 plat_arm_gic_pcpu_init(); 114 115 /* Enable the gic cpu interface */ 116 plat_arm_gic_cpuif_enable(); 117 118 /* Setup the CPU power down request interrupt for secondary core(s) */ 119 css_setup_cpu_pwr_down_intr(); 120 } 121 122 /******************************************************************************* 123 * Common function called while turning a cpu off or suspending it. It is called 124 * from css_off() or css_suspend() when these functions in turn are called for 125 * power domain at the highest power level which will be powered down. It 126 * performs the actions common to the OFF and SUSPEND calls. 127 ******************************************************************************/ 128 static void css_power_down_common(const psci_power_state_t *target_state) 129 { 130 /* Prevent interrupts from spuriously waking up this cpu */ 131 plat_arm_gic_cpuif_disable(); 132 133 /* Cluster is to be turned off, so disable coherency */ 134 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 135 plat_arm_interconnect_exit_coherency(); 136 } 137 138 /******************************************************************************* 139 * Handler called when a power domain is about to be turned off. The 140 * target_state encodes the power state that each level should transition to. 141 ******************************************************************************/ 142 void css_pwr_domain_off(const psci_power_state_t *target_state) 143 { 144 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 145 css_power_down_common(target_state); 146 css_scp_off(target_state); 147 } 148 149 /******************************************************************************* 150 * Handler called when a power domain is about to be suspended. The 151 * target_state encodes the power state that each level should transition to. 152 ******************************************************************************/ 153 void css_pwr_domain_suspend(const psci_power_state_t *target_state) 154 { 155 /* 156 * CSS currently supports retention only at cpu level. Just return 157 * as nothing is to be done for retention. 158 */ 159 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 160 return; 161 162 163 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 164 css_power_down_common(target_state); 165 166 /* Perform system domain state saving if issuing system suspend */ 167 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 168 arm_system_pwr_domain_save(); 169 170 /* Power off the Redistributor after having saved its context */ 171 plat_arm_gic_redistif_off(); 172 } 173 174 css_scp_suspend(target_state); 175 } 176 177 /******************************************************************************* 178 * Handler called when a power domain has just been powered on after 179 * having been suspended earlier. The target_state encodes the low power state 180 * that each level has woken up from. 181 * TODO: At the moment we reuse the on finisher and reinitialize the secure 182 * context. Need to implement a separate suspend finisher. 183 ******************************************************************************/ 184 void css_pwr_domain_suspend_finish( 185 const psci_power_state_t *target_state) 186 { 187 /* Return as nothing is to be done on waking up from retention. */ 188 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 189 return; 190 191 /* Perform system domain restore if woken up from system suspend */ 192 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) 193 /* 194 * At this point, the Distributor must be powered on to be ready 195 * to have its state restored. The Redistributor will be powered 196 * on as part of gicv3_rdistif_init_restore. 197 */ 198 arm_system_pwr_domain_resume(); 199 200 css_pwr_domain_on_finisher_common(target_state); 201 202 /* Enable the gic cpu interface */ 203 plat_arm_gic_cpuif_enable(); 204 } 205 206 /******************************************************************************* 207 * Handlers to shutdown/reboot the system 208 ******************************************************************************/ 209 void __dead2 css_system_off(void) 210 { 211 css_scp_sys_shutdown(); 212 } 213 214 void __dead2 css_system_reset(void) 215 { 216 css_scp_sys_reboot(); 217 } 218 219 /******************************************************************************* 220 * Handler called when the CPU power domain is about to enter standby. 221 ******************************************************************************/ 222 void css_cpu_standby(plat_local_state_t cpu_state) 223 { 224 unsigned int scr; 225 226 assert(cpu_state == ARM_LOCAL_STATE_RET); 227 228 scr = read_scr_el3(); 229 /* 230 * Enable the Non secure interrupt to wake the CPU. 231 * In GICv3 affinity routing mode, the non secure group1 interrupts use 232 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. 233 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 234 * routing mode. 235 */ 236 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 237 isb(); 238 dsb(); 239 wfi(); 240 241 /* 242 * Restore SCR to the original value, synchronisation of scr_el3 is 243 * done by eret while el3_exit to save some execution cycles. 244 */ 245 write_scr_el3(scr); 246 } 247 248 /******************************************************************************* 249 * Handler called to return the 'req_state' for system suspend. 250 ******************************************************************************/ 251 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) 252 { 253 unsigned int i; 254 255 /* 256 * System Suspend is supported only if the system power domain node 257 * is implemented. 258 */ 259 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); 260 261 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 262 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 263 } 264 265 /******************************************************************************* 266 * Handler to query CPU/cluster power states from SCP 267 ******************************************************************************/ 268 int css_node_hw_state(u_register_t mpidr, unsigned int power_level) 269 { 270 return css_scp_get_power_state(mpidr, power_level); 271 } 272 273 /* 274 * The system power domain suspend is only supported only via 275 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 276 * will be downgraded to the lower level. 277 */ 278 static int css_validate_power_state(unsigned int power_state, 279 psci_power_state_t *req_state) 280 { 281 int rc; 282 rc = arm_validate_power_state(power_state, req_state); 283 284 /* 285 * Ensure that we don't overrun the pwr_domain_state array in the case 286 * where the platform supported max power level is less than the system 287 * power level 288 */ 289 290 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) 291 292 /* 293 * Ensure that the system power domain level is never suspended 294 * via PSCI CPU SUSPEND API. Currently system suspend is only 295 * supported via PSCI SYSTEM SUSPEND API. 296 */ 297 298 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = 299 ARM_LOCAL_STATE_RUN; 300 #endif 301 302 return rc; 303 } 304 305 /* 306 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the 307 * `css_validate_power_state`, we do not downgrade the system power 308 * domain level request in `power_state` as it will be used to query the 309 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 310 */ 311 static int css_translate_power_state_by_mpidr(u_register_t mpidr, 312 unsigned int power_state, 313 psci_power_state_t *output_state) 314 { 315 return arm_validate_power_state(power_state, output_state); 316 } 317 318 /* 319 * Setup the SGI interrupt that will be used trigger the execution of power 320 * down sequence for all the secondary cores. This interrupt is setup to be 321 * handled in EL3 context at a priority defined by the platform. 322 */ 323 void css_setup_cpu_pwr_down_intr(void) 324 { 325 #if CSS_SYSTEM_GRACEFUL_RESET 326 plat_ic_set_interrupt_type(CSS_CPU_PWR_DOWN_REQ_INTR, INTR_TYPE_EL3); 327 plat_ic_set_interrupt_priority(CSS_CPU_PWR_DOWN_REQ_INTR, 328 PLAT_REBOOT_PRI); 329 plat_ic_enable_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); 330 #endif 331 } 332 333 /* 334 * For a graceful shutdown/reboot, each CPU in the system should do their power 335 * down sequence. On a PSCI shutdown/reboot request, only one CPU gets an 336 * opportunity to do the powerdown sequence. To achieve graceful reset, of all 337 * cores in the system, the CPU gets the opportunity raise warm reboot SGI to 338 * rest of the CPUs which are online. Add handler for the reboot SGI where the 339 * rest of the CPU execute the powerdown sequence. 340 */ 341 int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, 342 void *handle, void *cookie) 343 { 344 assert(intr_raw == CSS_CPU_PWR_DOWN_REQ_INTR); 345 346 /* Deactivate warm reboot SGI */ 347 plat_ic_end_of_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); 348 349 /* 350 * Disable GIC CPU interface to prevent pending interrupt from waking 351 * up the AP from WFI. 352 */ 353 plat_arm_gic_cpuif_disable(); 354 plat_arm_gic_redistif_off(); 355 356 psci_pwrdown_cpu(PLAT_MAX_PWR_LVL); 357 358 dmbsy(); 359 360 wfi(); 361 return 0; 362 } 363 364 /******************************************************************************* 365 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 366 * platform will take care of registering the handlers with PSCI. 367 ******************************************************************************/ 368 plat_psci_ops_t plat_arm_psci_pm_ops = { 369 .pwr_domain_on = css_pwr_domain_on, 370 .pwr_domain_on_finish = css_pwr_domain_on_finish, 371 .pwr_domain_on_finish_late = css_pwr_domain_on_finish_late, 372 .pwr_domain_off = css_pwr_domain_off, 373 .cpu_standby = css_cpu_standby, 374 .pwr_domain_suspend = css_pwr_domain_suspend, 375 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 376 .system_off = css_system_off, 377 .system_reset = css_system_reset, 378 .validate_power_state = css_validate_power_state, 379 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 380 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr, 381 .get_node_hw_state = css_node_hw_state, 382 .get_sys_suspend_power_state = css_get_sys_suspend_power_state, 383 384 #if defined(PLAT_ARM_MEM_PROT_ADDR) 385 .mem_protect_chk = arm_psci_mem_protect_chk, 386 .read_mem_protect = arm_psci_read_mem_protect, 387 .write_mem_protect = arm_nor_psci_write_mem_protect, 388 #endif 389 #if CSS_USE_SCMI_SDS_DRIVER 390 .system_reset2 = css_system_reset2, 391 #endif 392 }; 393