1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <bl31/interrupt_mgmt.h> 13 #include <common/debug.h> 14 #include <drivers/arm/css/css_scp.h> 15 #include <drivers/arm/css/dsu.h> 16 #include <lib/cassert.h> 17 #include <plat/arm/common/plat_arm.h> 18 19 #include <plat/common/platform.h> 20 21 #include <plat/arm/css/common/css_pm.h> 22 23 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ 24 #pragma weak plat_arm_psci_pm_ops 25 26 #if ARM_RECOM_STATE_ID_ENC 27 /* 28 * The table storing the valid idle power states. Ensure that the 29 * array entries are populated in ascending order of state-id to 30 * enable us to use binary search during power state validation. 31 * The table must be terminated by a NULL entry. 32 */ 33 const unsigned int arm_pm_idle_states[] = { 34 /* State-id - 0x001 */ 35 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 36 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 37 /* State-id - 0x002 */ 38 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 39 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 40 /* State-id - 0x022 */ 41 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 42 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 43 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 44 /* State-id - 0x222 */ 45 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 46 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 47 #endif 48 0, 49 }; 50 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 51 52 /* 53 * All the power management helpers in this file assume at least cluster power 54 * level is supported. 55 */ 56 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, 57 assert_max_pwr_lvl_supported_mismatch); 58 59 /* 60 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL 61 * assumed by the CSS layer. 62 */ 63 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL, 64 assert_max_pwr_lvl_higher_than_css_sys_lvl); 65 66 /******************************************************************************* 67 * Handler called when a power domain is about to be turned on. The 68 * level and mpidr determine the affinity instance. 69 ******************************************************************************/ 70 int css_pwr_domain_on(u_register_t mpidr) 71 { 72 css_scp_on(mpidr); 73 74 return PSCI_E_SUCCESS; 75 } 76 77 static void css_pwr_domain_on_finisher_common( 78 const psci_power_state_t *target_state) 79 { 80 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 81 82 /* 83 * Perform the common cluster specific operations i.e enable coherency 84 * if this cluster was off. 85 */ 86 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { 87 #if PRESERVE_DSU_PMU_REGS 88 cluster_on_dsu_pmu_context_restore(); 89 #endif 90 plat_arm_interconnect_enter_coherency(); 91 } 92 } 93 94 /******************************************************************************* 95 * Handler called when a power level has just been powered on after 96 * being turned off earlier. The target_state encodes the low power state that 97 * each level has woken up from. This handler would never be invoked with 98 * the system power domain uninitialized as either the primary would have taken 99 * care of it as part of cold boot or the first core awakened from system 100 * suspend would have already initialized it. 101 ******************************************************************************/ 102 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 103 { 104 /* Assert that the system power domain need not be initialized */ 105 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 106 107 css_pwr_domain_on_finisher_common(target_state); 108 } 109 110 /******************************************************************************* 111 * Handler called when a power domain has just been powered on and the cpu 112 * and its cluster are fully participating in coherent transaction on the 113 * interconnect. Data cache must be enabled for CPU at this point. 114 ******************************************************************************/ 115 void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) 116 { 117 /* Setup the CPU power down request interrupt for secondary core(s) */ 118 css_setup_cpu_pwr_down_intr(); 119 } 120 121 /******************************************************************************* 122 * Common function called while turning a cpu off or suspending it. It is called 123 * from css_off() or css_suspend() when these functions in turn are called for 124 * power domain at the highest power level which will be powered down. It 125 * performs the actions common to the OFF and SUSPEND calls. 126 ******************************************************************************/ 127 static void css_power_down_common(const psci_power_state_t *target_state) 128 { 129 /* Cluster is to be turned off, so disable coherency */ 130 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { 131 #if PRESERVE_DSU_PMU_REGS 132 cluster_off_dsu_pmu_context_save(); 133 #endif 134 plat_arm_interconnect_exit_coherency(); 135 } 136 } 137 138 /******************************************************************************* 139 * Handler called when a power domain is about to be turned off. The 140 * target_state encodes the power state that each level should transition to. 141 ******************************************************************************/ 142 void css_pwr_domain_off(const psci_power_state_t *target_state) 143 { 144 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 145 css_power_down_common(target_state); 146 css_scp_off(target_state); 147 } 148 149 /******************************************************************************* 150 * Handler called when a power domain is about to be suspended. The 151 * target_state encodes the power state that each level should transition to. 152 ******************************************************************************/ 153 void css_pwr_domain_suspend(const psci_power_state_t *target_state) 154 { 155 /* 156 * CSS currently supports retention only at cpu level. Just return 157 * as nothing is to be done for retention. 158 */ 159 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 160 return; 161 162 163 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 164 css_power_down_common(target_state); 165 166 /* Perform system domain state saving if issuing system suspend */ 167 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 168 arm_system_pwr_domain_save(); 169 170 /* Power off the Redistributor after having saved its context */ 171 gic_pcpu_off(plat_my_core_pos()); 172 } 173 174 css_scp_suspend(target_state); 175 } 176 177 /******************************************************************************* 178 * Handler called when a power domain has just been powered on after 179 * having been suspended earlier. The target_state encodes the low power state 180 * that each level has woken up from. 181 * TODO: At the moment we reuse the on finisher and reinitialize the secure 182 * context. Need to implement a separate suspend finisher. 183 ******************************************************************************/ 184 void css_pwr_domain_suspend_finish( 185 const psci_power_state_t *target_state) 186 { 187 /* Return as nothing is to be done on waking up from retention. */ 188 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 189 return; 190 191 /* Perform system domain restore if woken up from system suspend */ 192 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) 193 /* 194 * At this point, the Distributor must be powered on to be ready 195 * to have its state restored. The Redistributor will be powered 196 * on as part of gicv3_rdistif_init_restore. 197 */ 198 arm_system_pwr_domain_resume(); 199 200 css_pwr_domain_on_finisher_common(target_state); 201 } 202 203 /******************************************************************************* 204 * Handlers to shutdown/reboot the system 205 ******************************************************************************/ 206 void css_system_off(void) 207 { 208 css_scp_sys_shutdown(); 209 } 210 211 void css_system_reset(void) 212 { 213 css_scp_sys_reboot(); 214 } 215 216 /******************************************************************************* 217 * Handler called when the CPU power domain is about to enter standby. 218 ******************************************************************************/ 219 void css_cpu_standby(plat_local_state_t cpu_state) 220 { 221 unsigned int scr; 222 223 assert(cpu_state == ARM_LOCAL_STATE_RET); 224 225 scr = read_scr_el3(); 226 /* 227 * Enable the Non secure interrupt to wake the CPU. 228 * In GICv3 affinity routing mode, the non secure group1 interrupts use 229 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. 230 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 231 * routing mode. 232 */ 233 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 234 isb(); 235 dsb(); 236 wfi(); 237 238 /* 239 * Restore SCR to the original value, synchronisation of scr_el3 is 240 * done by eret while el3_exit to save some execution cycles. 241 */ 242 write_scr_el3(scr); 243 } 244 245 /******************************************************************************* 246 * Handler called to return the 'req_state' for system suspend. 247 ******************************************************************************/ 248 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) 249 { 250 unsigned int i; 251 252 /* 253 * System Suspend is supported only if the system power domain node 254 * is implemented. 255 */ 256 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); 257 258 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 259 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 260 } 261 262 /******************************************************************************* 263 * Handler to query CPU/cluster power states from SCP 264 ******************************************************************************/ 265 int css_node_hw_state(u_register_t mpidr, unsigned int power_level) 266 { 267 return css_scp_get_power_state(mpidr, power_level); 268 } 269 270 /* 271 * The system power domain suspend is only supported only via 272 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 273 * will be downgraded to the lower level. 274 */ 275 static int css_validate_power_state(unsigned int power_state, 276 psci_power_state_t *req_state) 277 { 278 int rc; 279 rc = arm_validate_power_state(power_state, req_state); 280 281 /* 282 * Ensure that we don't overrun the pwr_domain_state array in the case 283 * where the platform supported max power level is less than the system 284 * power level 285 */ 286 287 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) 288 289 /* 290 * Ensure that the system power domain level is never suspended 291 * via PSCI CPU SUSPEND API. Currently system suspend is only 292 * supported via PSCI SYSTEM SUSPEND API. 293 */ 294 295 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = 296 ARM_LOCAL_STATE_RUN; 297 #endif 298 299 return rc; 300 } 301 302 /* 303 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the 304 * `css_validate_power_state`, we do not downgrade the system power 305 * domain level request in `power_state` as it will be used to query the 306 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 307 */ 308 static int css_translate_power_state_by_mpidr(u_register_t mpidr, 309 unsigned int power_state, 310 psci_power_state_t *output_state) 311 { 312 return arm_validate_power_state(power_state, output_state); 313 } 314 315 /* 316 * Setup the SGI interrupt that will be used trigger the execution of power 317 * down sequence for all the secondary cores. This interrupt is setup to be 318 * handled in EL3 context at a priority defined by the platform. 319 */ 320 void css_setup_cpu_pwr_down_intr(void) 321 { 322 #if CSS_SYSTEM_GRACEFUL_RESET 323 plat_ic_set_interrupt_type(CSS_CPU_PWR_DOWN_REQ_INTR, INTR_TYPE_EL3); 324 plat_ic_set_interrupt_priority(CSS_CPU_PWR_DOWN_REQ_INTR, 325 PLAT_REBOOT_PRI); 326 plat_ic_enable_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); 327 #endif 328 } 329 330 /* 331 * For a graceful shutdown/reboot, each CPU in the system should do their power 332 * down sequence. On a PSCI shutdown/reboot request, only one CPU gets an 333 * opportunity to do the powerdown sequence. To achieve graceful reset, of all 334 * cores in the system, the CPU gets the opportunity raise warm reboot SGI to 335 * rest of the CPUs which are online. Add handler for the reboot SGI where the 336 * rest of the CPU execute the powerdown sequence. 337 */ 338 int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, 339 void *handle, void *cookie) 340 { 341 unsigned int core_pos = plat_my_core_pos(); 342 343 assert(intr_raw == CSS_CPU_PWR_DOWN_REQ_INTR); 344 345 /* Deactivate warm reboot SGI */ 346 plat_ic_end_of_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); 347 348 /* 349 * Disable GIC CPU interface to prevent pending interrupt from waking 350 * up the AP from WFI. 351 */ 352 gic_cpuif_disable(core_pos); 353 gic_pcpu_off(core_pos); 354 355 psci_pwrdown_cpu_start(PLAT_MAX_PWR_LVL); 356 357 psci_pwrdown_cpu_end_terminal(); 358 return 0; 359 } 360 361 /******************************************************************************* 362 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 363 * platform will take care of registering the handlers with PSCI. 364 ******************************************************************************/ 365 plat_psci_ops_t plat_arm_psci_pm_ops = { 366 .pwr_domain_on = css_pwr_domain_on, 367 .pwr_domain_on_finish = css_pwr_domain_on_finish, 368 .pwr_domain_on_finish_late = css_pwr_domain_on_finish_late, 369 .pwr_domain_off = css_pwr_domain_off, 370 .cpu_standby = css_cpu_standby, 371 .pwr_domain_suspend = css_pwr_domain_suspend, 372 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 373 .system_off = css_system_off, 374 .system_reset = css_system_reset, 375 .validate_power_state = css_validate_power_state, 376 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 377 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr, 378 .get_node_hw_state = css_node_hw_state, 379 .get_sys_suspend_power_state = css_get_sys_suspend_power_state, 380 381 #if defined(PLAT_ARM_MEM_PROT_ADDR) 382 .mem_protect_chk = arm_psci_mem_protect_chk, 383 .read_mem_protect = arm_psci_read_mem_protect, 384 .write_mem_protect = arm_nor_psci_write_mem_protect, 385 #endif 386 #if CSS_USE_SCMI_SDS_DRIVER 387 .system_reset2 = css_system_reset2, 388 #endif 389 }; 390