1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <arm_def.h> 34 #include <assert.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <debug.h> 38 #include <mmio.h> 39 #include <plat_arm.h> 40 #include <platform.h> 41 42 43 /* 44 * The next 3 constants identify the extents of the code, RO data region and the 45 * limit of the BL31 image. These addresses are used by the MMU setup code and 46 * therefore they must be page-aligned. It is the responsibility of the linker 47 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 48 * refer to page-aligned addresses. 49 */ 50 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 51 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 52 #define BL31_END (unsigned long)(&__BL31_END__) 53 54 #if USE_COHERENT_MEM 55 /* 56 * The next 2 constants identify the extents of the coherent memory region. 57 * These addresses are used by the MMU setup code and therefore they must be 58 * page-aligned. It is the responsibility of the linker script to ensure that 59 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 60 * refer to page-aligned addresses. 61 */ 62 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 63 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 64 #endif 65 66 /* 67 * Placeholder variables for copying the arguments that have been passed to 68 * BL31 from BL2. 69 */ 70 static entry_point_info_t bl32_image_ep_info; 71 static entry_point_info_t bl33_image_ep_info; 72 73 74 /* Weak definitions may be overridden in specific ARM standard platform */ 75 #pragma weak bl31_early_platform_setup 76 #pragma weak bl31_platform_setup 77 #pragma weak bl31_plat_arch_setup 78 #pragma weak bl31_plat_get_next_image_ep_info 79 #pragma weak plat_get_syscnt_freq 80 81 82 /******************************************************************************* 83 * Return a pointer to the 'entry_point_info' structure of the next image for the 84 * security state specified. BL33 corresponds to the non-secure image type 85 * while BL32 corresponds to the secure image type. A NULL pointer is returned 86 * if the image does not exist. 87 ******************************************************************************/ 88 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 89 { 90 entry_point_info_t *next_image_info; 91 92 assert(sec_state_is_valid(type)); 93 next_image_info = (type == NON_SECURE) 94 ? &bl33_image_ep_info : &bl32_image_ep_info; 95 /* 96 * None of the images on the ARM development platforms can have 0x0 97 * as the entrypoint 98 */ 99 if (next_image_info->pc) 100 return next_image_info; 101 else 102 return NULL; 103 } 104 105 /******************************************************************************* 106 * Perform any BL31 early platform setup common to ARM standard platforms. 107 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 108 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 109 * done before the MMU is initialized so that the memory layout can be used 110 * while creating page tables. BL2 has flushed this information to memory, so 111 * we are guaranteed to pick up good data. 112 ******************************************************************************/ 113 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, 114 void *plat_params_from_bl2) 115 { 116 /* Initialize the console to provide early debug support */ 117 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 118 ARM_CONSOLE_BAUDRATE); 119 120 #if RESET_TO_BL31 121 /* There are no parameters from BL2 if BL31 is a reset vector */ 122 assert(from_bl2 == NULL); 123 assert(plat_params_from_bl2 == NULL); 124 125 #ifdef BL32_BASE 126 /* Populate entry point information for BL32 */ 127 SET_PARAM_HEAD(&bl32_image_ep_info, 128 PARAM_EP, 129 VERSION_1, 130 0); 131 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 132 bl32_image_ep_info.pc = BL32_BASE; 133 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 134 #endif /* BL32_BASE */ 135 136 /* Populate entry point information for BL33 */ 137 SET_PARAM_HEAD(&bl33_image_ep_info, 138 PARAM_EP, 139 VERSION_1, 140 0); 141 /* 142 * Tell BL31 where the non-trusted software image 143 * is located and the entry state information 144 */ 145 #ifdef BL33_BASE 146 bl33_image_ep_info.pc = BL33_BASE; 147 #else 148 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 149 #endif 150 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 151 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 152 153 #else 154 /* 155 * Check params passed from BL2 should not be NULL, 156 */ 157 assert(from_bl2 != NULL); 158 assert(from_bl2->h.type == PARAM_BL31); 159 assert(from_bl2->h.version >= VERSION_1); 160 /* 161 * In debug builds, we pass a special value in 'plat_params_from_bl2' 162 * to verify platform parameters from BL2 to BL31. 163 * In release builds, it's not used. 164 */ 165 assert(((unsigned long long)plat_params_from_bl2) == 166 ARM_BL31_PLAT_PARAM_VAL); 167 168 /* 169 * Copy BL32 (if populated by BL2) and BL33 entry point information. 170 * They are stored in Secure RAM, in BL2's address space. 171 */ 172 if (from_bl2->bl32_ep_info) 173 bl32_image_ep_info = *from_bl2->bl32_ep_info; 174 bl33_image_ep_info = *from_bl2->bl33_ep_info; 175 #endif 176 } 177 178 void bl31_early_platform_setup(bl31_params_t *from_bl2, 179 void *plat_params_from_bl2) 180 { 181 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); 182 183 /* 184 * Initialize Interconnect for this cluster during cold boot. 185 * No need for locks as no other CPU is active. 186 */ 187 plat_arm_interconnect_init(); 188 189 /* 190 * Enable Interconnect coherency for the primary CPU's cluster. 191 * Earlier bootloader stages might already do this (e.g. Trusted 192 * Firmware's BL1 does it) but we can't assume so. There is no harm in 193 * executing this code twice anyway. 194 * Platform specific PSCI code will enable coherency for other 195 * clusters. 196 */ 197 plat_arm_interconnect_enter_coherency(); 198 } 199 200 /******************************************************************************* 201 * Perform any BL31 platform setup common to ARM standard platforms 202 ******************************************************************************/ 203 void arm_bl31_platform_setup(void) 204 { 205 /* Initialize the GIC driver, cpu and distributor interfaces */ 206 plat_arm_gic_driver_init(); 207 plat_arm_gic_init(); 208 209 #if RESET_TO_BL31 210 /* 211 * Do initial security configuration to allow DRAM/device access 212 * (if earlier BL has not already done so). 213 */ 214 plat_arm_security_setup(); 215 216 #endif /* RESET_TO_BL31 */ 217 218 /* Enable and initialize the System level generic timer */ 219 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 220 CNTCR_FCREQ(0) | CNTCR_EN); 221 222 /* Allow access to the System counter timer module */ 223 arm_configure_sys_timer(); 224 225 /* Initialize power controller before setting up topology */ 226 plat_arm_pwrc_setup(); 227 } 228 229 /******************************************************************************* 230 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 231 * standard platforms 232 ******************************************************************************/ 233 void arm_bl31_plat_runtime_setup(void) 234 { 235 /* Initialize the runtime console */ 236 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, 237 ARM_CONSOLE_BAUDRATE); 238 } 239 240 void bl31_platform_setup(void) 241 { 242 arm_bl31_platform_setup(); 243 } 244 245 void bl31_plat_runtime_setup(void) 246 { 247 arm_bl31_plat_runtime_setup(); 248 } 249 250 /******************************************************************************* 251 * Perform the very early platform specific architectural setup here. At the 252 * moment this is only intializes the mmu in a quick and dirty way. 253 ******************************************************************************/ 254 void arm_bl31_plat_arch_setup(void) 255 { 256 arm_configure_mmu_el3(BL31_RO_BASE, 257 (BL31_END - BL31_RO_BASE), 258 BL31_RO_BASE, 259 BL31_RO_LIMIT 260 #if USE_COHERENT_MEM 261 , BL31_COHERENT_RAM_BASE, 262 BL31_COHERENT_RAM_LIMIT 263 #endif 264 ); 265 } 266 267 void bl31_plat_arch_setup(void) 268 { 269 arm_bl31_plat_arch_setup(); 270 } 271 272 uint64_t plat_get_syscnt_freq(void) 273 { 274 uint64_t counter_base_frequency; 275 276 /* Read the frequency from Frequency modes table */ 277 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 278 279 /* The first entry of the frequency modes table must not be 0 */ 280 if (counter_base_frequency == 0) 281 panic(); 282 283 return counter_base_frequency; 284 } 285