1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <lib/debugfs.h> 16 #include <lib/extensions/ras.h> 17 #include <lib/fconf/fconf.h> 18 #include <lib/gpt_rme/gpt_rme.h> 19 #include <lib/mmio.h> 20 #if TRANSFER_LIST 21 #include <lib/transfer_list.h> 22 #endif 23 #include <lib/xlat_tables/xlat_tables_compat.h> 24 #include <plat/arm/common/plat_arm.h> 25 #include <plat/common/platform.h> 26 #include <platform_def.h> 27 28 struct transfer_list_header *secure_tl; 29 struct transfer_list_header *ns_tl __unused; 30 31 /* 32 * Placeholder variables for copying the arguments that have been passed to 33 * BL31 from BL2. 34 */ 35 static entry_point_info_t bl32_image_ep_info; 36 static entry_point_info_t bl33_image_ep_info; 37 #if ENABLE_RME 38 static entry_point_info_t rmm_image_ep_info; 39 #endif 40 41 #if !RESET_TO_BL31 42 /* 43 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 44 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 45 */ 46 #if TRANSFER_LIST 47 CASSERT(BL31_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl31_base_overflows); 48 #else 49 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 50 #endif /* TRANSFER_LIST */ 51 #endif /* RESET_TO_BL31 */ 52 53 /* Weak definitions may be overridden in specific ARM standard platform */ 54 #pragma weak bl31_early_platform_setup2 55 #pragma weak bl31_platform_setup 56 #pragma weak bl31_plat_arch_setup 57 #pragma weak bl31_plat_get_next_image_ep_info 58 #pragma weak bl31_plat_runtime_setup 59 60 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 61 BL31_START, \ 62 BL31_END - BL31_START, \ 63 MT_MEMORY | MT_RW | EL3_PAS) 64 #if RECLAIM_INIT_CODE 65 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 66 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 67 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 68 69 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 70 ~(PAGE_SIZE - 1)) 71 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 72 ~(PAGE_SIZE - 1)) 73 74 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 75 BL_INIT_CODE_BASE, \ 76 BL_INIT_CODE_END \ 77 - BL_INIT_CODE_BASE, \ 78 MT_CODE | EL3_PAS) 79 #endif 80 81 #if SEPARATE_NOBITS_REGION 82 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 83 BL31_NOBITS_BASE, \ 84 BL31_NOBITS_LIMIT \ 85 - BL31_NOBITS_BASE, \ 86 MT_MEMORY | MT_RW | EL3_PAS) 87 88 #endif 89 /******************************************************************************* 90 * Return a pointer to the 'entry_point_info' structure of the next image for the 91 * security state specified. BL33 corresponds to the non-secure image type 92 * while BL32 corresponds to the secure image type. A NULL pointer is returned 93 * if the image does not exist. 94 ******************************************************************************/ 95 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 96 { 97 entry_point_info_t *next_image_info; 98 99 assert(sec_state_is_valid(type)); 100 if (type == NON_SECURE) { 101 #if TRANSFER_LIST && !RESET_TO_BL31 102 next_image_info = transfer_list_set_handoff_args( 103 ns_tl, &bl33_image_ep_info); 104 #else 105 next_image_info = &bl33_image_ep_info; 106 #endif 107 } 108 #if ENABLE_RME 109 else if (type == REALM) { 110 next_image_info = &rmm_image_ep_info; 111 } 112 #endif 113 else { 114 next_image_info = &bl32_image_ep_info; 115 } 116 117 /* 118 * None of the images on the ARM development platforms can have 0x0 119 * as the entrypoint 120 */ 121 if (next_image_info->pc) 122 return next_image_info; 123 else 124 return NULL; 125 } 126 127 /******************************************************************************* 128 * Perform any BL31 early platform setup common to ARM standard platforms. 129 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 130 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 131 * done before the MMU is initialized so that the memory layout can be used 132 * while creating page tables. BL2 has flushed this information to memory, so 133 * we are guaranteed to pick up good data. 134 ******************************************************************************/ 135 #if TRANSFER_LIST 136 void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 137 u_register_t arg2, u_register_t arg3) 138 { 139 #if RESET_TO_BL31 140 /* Populate entry point information for BL33 */ 141 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 142 /* 143 * Tell BL31 where the non-trusted software image 144 * is located and the entry state information 145 */ 146 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 147 148 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 149 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 150 151 bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET; 152 bl33_image_ep_info.args.arg1 = 153 TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION); 154 bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE; 155 #else 156 struct transfer_list_entry *te = NULL; 157 struct entry_point_info *ep; 158 159 secure_tl = (struct transfer_list_header *)arg3; 160 161 /* 162 * Populate the global entry point structures used to execute subsequent 163 * images. 164 */ 165 while ((te = transfer_list_next(secure_tl, te)) != NULL) { 166 ep = transfer_list_entry_data(te); 167 168 if (te->tag_id == TL_TAG_EXEC_EP_INFO64) { 169 switch (GET_SECURITY_STATE(ep->h.attr)) { 170 case NON_SECURE: 171 bl33_image_ep_info = *ep; 172 break; 173 #if ENABLE_RME 174 case REALM: 175 rmm_image_ep_info = *ep; 176 break; 177 #endif 178 case SECURE: 179 bl32_image_ep_info = *ep; 180 break; 181 default: 182 ERROR("Unrecognized Image Security State %lu\n", 183 GET_SECURITY_STATE(ep->h.attr)); 184 panic(); 185 } 186 } 187 } 188 #endif /* RESET_TO_BL31 */ 189 } 190 #else 191 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 192 uintptr_t hw_config, void *plat_params_from_bl2) 193 { 194 /* Initialize the console to provide early debug support */ 195 arm_console_boot_init(); 196 197 #if RESET_TO_BL31 198 /* There are no parameters from BL2 if BL31 is a reset vector */ 199 assert(from_bl2 == NULL); 200 assert(plat_params_from_bl2 == NULL); 201 202 # ifdef BL32_BASE 203 /* Populate entry point information for BL32 */ 204 SET_PARAM_HEAD(&bl32_image_ep_info, 205 PARAM_EP, 206 VERSION_1, 207 0); 208 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 209 bl32_image_ep_info.pc = BL32_BASE; 210 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 211 212 #if defined(SPD_spmd) 213 bl32_image_ep_info.args.arg0 = ARM_SPMC_MANIFEST_BASE; 214 #endif 215 216 # endif /* BL32_BASE */ 217 218 /* Populate entry point information for BL33 */ 219 SET_PARAM_HEAD(&bl33_image_ep_info, 220 PARAM_EP, 221 VERSION_1, 222 0); 223 /* 224 * Tell BL31 where the non-trusted software image 225 * is located and the entry state information 226 */ 227 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 228 229 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 230 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 231 232 #if ENABLE_RME 233 /* 234 * Populate entry point information for RMM. 235 * Only PC needs to be set as other fields are determined by RMMD. 236 */ 237 rmm_image_ep_info.pc = RMM_BASE; 238 #endif /* ENABLE_RME */ 239 240 #else /* RESET_TO_BL31 */ 241 242 /* 243 * In debug builds, we pass a special value in 'plat_params_from_bl2' 244 * to verify platform parameters from BL2 to BL31. 245 * In release builds, it's not used. 246 */ 247 assert(((unsigned long long)plat_params_from_bl2) == 248 ARM_BL31_PLAT_PARAM_VAL); 249 250 /* 251 * Check params passed from BL2 should not be NULL, 252 */ 253 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 254 assert(params_from_bl2 != NULL); 255 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 256 assert(params_from_bl2->h.version >= VERSION_2); 257 258 bl_params_node_t *bl_params = params_from_bl2->head; 259 260 /* 261 * Copy BL33, BL32 and RMM (if present), entry point information. 262 * They are stored in Secure RAM, in BL2's address space. 263 */ 264 while (bl_params != NULL) { 265 if (bl_params->image_id == BL32_IMAGE_ID) { 266 bl32_image_ep_info = *bl_params->ep_info; 267 #if SPMC_AT_EL3 268 /* 269 * Populate the BL32 image base, size and max limit in 270 * the entry point information, since there is no 271 * platform function to retrieve them in generic 272 * code. We choose arg2, arg3 and arg4 since the generic 273 * code uses arg1 for stashing the SP manifest size. The 274 * SPMC setup uses these arguments to update SP manifest 275 * with actual SP's base address and it size. 276 */ 277 bl32_image_ep_info.args.arg2 = 278 bl_params->image_info->image_base; 279 bl32_image_ep_info.args.arg3 = 280 bl_params->image_info->image_size; 281 bl32_image_ep_info.args.arg4 = 282 bl_params->image_info->image_base + 283 bl_params->image_info->image_max_size; 284 #endif 285 } 286 #if ENABLE_RME 287 else if (bl_params->image_id == RMM_IMAGE_ID) { 288 rmm_image_ep_info = *bl_params->ep_info; 289 } 290 #endif 291 else if (bl_params->image_id == BL33_IMAGE_ID) { 292 bl33_image_ep_info = *bl_params->ep_info; 293 } 294 295 bl_params = bl_params->next_params_info; 296 } 297 298 if (bl33_image_ep_info.pc == 0U) 299 panic(); 300 #if ENABLE_RME 301 if (rmm_image_ep_info.pc == 0U) 302 panic(); 303 #endif 304 #endif /* RESET_TO_BL31 */ 305 306 # if ARM_LINUX_KERNEL_AS_BL33 307 /* 308 * According to the file ``Documentation/arm64/booting.txt`` of the 309 * Linux kernel tree, Linux expects the physical address of the device 310 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 311 * must be 0. 312 * Repurpose the option to load Hafnium hypervisor in the normal world. 313 * It expects its manifest address in x0. This is essentially the linux 314 * dts (passed to the primary VM) by adding 'hypervisor' and chosen 315 * nodes specifying the Hypervisor configuration. 316 */ 317 #if RESET_TO_BL31 318 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 319 #else 320 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config; 321 #endif 322 bl33_image_ep_info.args.arg1 = 0U; 323 bl33_image_ep_info.args.arg2 = 0U; 324 bl33_image_ep_info.args.arg3 = 0U; 325 # endif 326 } 327 #endif 328 329 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 330 u_register_t arg2, u_register_t arg3) 331 { 332 #if TRANSFER_LIST 333 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 334 #else 335 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 336 #endif 337 338 /* 339 * Initialize Interconnect for this cluster during cold boot. 340 * No need for locks as no other CPU is active. 341 */ 342 plat_arm_interconnect_init(); 343 344 /* 345 * Enable Interconnect coherency for the primary CPU's cluster. 346 * Earlier bootloader stages might already do this (e.g. Trusted 347 * Firmware's BL1 does it) but we can't assume so. There is no harm in 348 * executing this code twice anyway. 349 * Platform specific PSCI code will enable coherency for other 350 * clusters. 351 */ 352 plat_arm_interconnect_enter_coherency(); 353 } 354 355 /******************************************************************************* 356 * Perform any BL31 platform setup common to ARM standard platforms 357 ******************************************************************************/ 358 void arm_bl31_platform_setup(void) 359 { 360 struct transfer_list_entry *te __unused; 361 362 #if TRANSFER_LIST && !RESET_TO_BL31 363 ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE, 364 PLAT_ARM_FW_HANDOFF_SIZE); 365 if (ns_tl == NULL) { 366 ERROR("Non-secure transfer list initialisation failed!\n"); 367 panic(); 368 } 369 /* BL31 may modify the HW_CONFIG so defer copying it until later. */ 370 te = transfer_list_find(secure_tl, TL_TAG_FDT); 371 assert(te != NULL); 372 373 /* 374 * A pre-existing assumption is that FCONF is unsupported w/ RESET_TO_BL2 and 375 * RESET_TO_BL31. In the case of RESET_TO_BL31 this makes sense because there 376 * isn't a prior stage to load the device tree, but the reasoning for RESET_TO_BL2 is 377 * less clear. For the moment hardware properties that would normally be 378 * derived from the DT are statically defined. 379 */ 380 #if !RESET_TO_BL2 381 fconf_populate("HW_CONFIG", (uintptr_t)transfer_list_entry_data(te)); 382 #endif 383 384 te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size, 385 transfer_list_entry_data(te)); 386 assert(te != NULL); 387 #endif /* TRANSFER_LIST && !RESET_TO_BL31 */ 388 389 /* Initialize the GIC driver, cpu and distributor interfaces */ 390 plat_arm_gic_driver_init(); 391 plat_arm_gic_init(); 392 393 #if RESET_TO_BL31 394 /* 395 * Do initial security configuration to allow DRAM/device access 396 * (if earlier BL has not already done so). 397 */ 398 plat_arm_security_setup(); 399 400 #if defined(PLAT_ARM_MEM_PROT_ADDR) 401 arm_nor_psci_do_dyn_mem_protect(); 402 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 403 404 #endif /* RESET_TO_BL31 */ 405 406 /* Enable and initialize the System level generic timer */ 407 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 408 CNTCR_FCREQ(0U) | CNTCR_EN); 409 410 /* Allow access to the System counter timer module */ 411 arm_configure_sys_timer(); 412 413 /* Initialize power controller before setting up topology */ 414 plat_arm_pwrc_setup(); 415 416 #if ENABLE_FEAT_RAS && FFH_SUPPORT 417 ras_init(); 418 #endif 419 420 #if USE_DEBUGFS 421 debugfs_init(); 422 #endif /* USE_DEBUGFS */ 423 } 424 425 /******************************************************************************* 426 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 427 * standard platforms 428 ******************************************************************************/ 429 void arm_bl31_plat_runtime_setup(void) 430 { 431 struct transfer_list_entry *te __unused; 432 /* Initialize the runtime console */ 433 arm_console_runtime_init(); 434 435 #if TRANSFER_LIST && !RESET_TO_BL31 436 /* 437 * We assume BL31 has added all TE's required by BL33 at this stage, ensure 438 * that data is visible to all observers by performing a flush operation, so 439 * they can access the updated data even if caching is not enabled. 440 */ 441 flush_dcache_range((uintptr_t)ns_tl, ns_tl->size); 442 #endif /* TRANSFER_LIST && !RESET_TO_BL31 */ 443 444 #if RECLAIM_INIT_CODE 445 arm_free_init_memory(); 446 #endif 447 448 #if PLAT_RO_XLAT_TABLES 449 arm_xlat_make_tables_readonly(); 450 #endif 451 } 452 453 #if RECLAIM_INIT_CODE 454 /* 455 * Make memory for image boot time code RW to reclaim it as stack for the 456 * secondary cores, or RO where it cannot be reclaimed: 457 * 458 * |-------- INIT SECTION --------| 459 * ----------------------------------------- 460 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 461 * | STACK | STACK | STACK | SPACE | 462 * ----------------------------------------- 463 * <-------------------> <------> 464 * MAKE RW AND XN MAKE 465 * FOR STACKS RO AND XN 466 */ 467 void arm_free_init_memory(void) 468 { 469 int ret = 0; 470 471 if (BL_STACKS_END < BL_INIT_CODE_END) { 472 /* Reclaim some of the init section as stack if possible. */ 473 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 474 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 475 BL_STACKS_END - BL_INIT_CODE_BASE, 476 MT_RW_DATA); 477 } 478 /* Make the rest of the init section read-only. */ 479 ret |= xlat_change_mem_attributes(BL_STACKS_END, 480 BL_INIT_CODE_END - BL_STACKS_END, 481 MT_RO_DATA); 482 } else { 483 /* The stacks cover the init section, so reclaim it all. */ 484 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 485 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 486 MT_RW_DATA); 487 } 488 489 if (ret != 0) { 490 ERROR("Could not reclaim initialization code"); 491 panic(); 492 } 493 } 494 #endif 495 496 void __init bl31_platform_setup(void) 497 { 498 arm_bl31_platform_setup(); 499 } 500 501 void bl31_plat_runtime_setup(void) 502 { 503 arm_bl31_plat_runtime_setup(); 504 } 505 506 /******************************************************************************* 507 * Perform the very early platform specific architectural setup shared between 508 * ARM standard platforms. This only does basic initialization. Later 509 * architectural setup (bl31_arch_setup()) does not do anything platform 510 * specific. 511 ******************************************************************************/ 512 void __init arm_bl31_plat_arch_setup(void) 513 { 514 const mmap_region_t bl_regions[] = { 515 MAP_BL31_TOTAL, 516 #if ENABLE_RME 517 ARM_MAP_L0_GPT_REGION, 518 #endif 519 #if RECLAIM_INIT_CODE 520 MAP_BL_INIT_CODE, 521 #endif 522 #if SEPARATE_NOBITS_REGION 523 MAP_BL31_NOBITS, 524 #endif 525 ARM_MAP_BL_RO, 526 #if USE_ROMLIB 527 ARM_MAP_ROMLIB_CODE, 528 ARM_MAP_ROMLIB_DATA, 529 #endif 530 #if USE_COHERENT_MEM 531 ARM_MAP_BL_COHERENT_RAM, 532 #endif 533 {0} 534 }; 535 536 setup_page_tables(bl_regions, plat_arm_get_mmap()); 537 538 enable_mmu_el3(0); 539 540 #if ENABLE_RME 541 #if RESET_TO_BL31 542 /* initialize GPT only when RME is enabled. */ 543 assert(is_feat_rme_present()); 544 545 /* Initialise and enable granule protection after MMU. */ 546 arm_gpt_setup(); 547 #endif /* RESET_TO_BL31 */ 548 /* 549 * Initialise Granule Protection library and enable GPC for the primary 550 * processor. The tables have already been initialized by a previous BL 551 * stage, so there is no need to provide any PAS here. This function 552 * sets up pointers to those tables. 553 */ 554 if (gpt_runtime_init() < 0) { 555 ERROR("gpt_runtime_init() failed!\n"); 556 panic(); 557 } 558 #endif /* ENABLE_RME */ 559 560 arm_setup_romlib(); 561 } 562 563 void __init bl31_plat_arch_setup(void) 564 { 565 arm_bl31_plat_arch_setup(); 566 } 567