1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <arm_def.h> 34 #include <arm_gic.h> 35 #include <assert.h> 36 #include <bl_common.h> 37 #include <cci.h> 38 #include <console.h> 39 #include <debug.h> 40 #include <mmio.h> 41 #include <plat_arm.h> 42 #include <platform.h> 43 #include <platform_def.h> 44 45 46 /* 47 * The next 3 constants identify the extents of the code, RO data region and the 48 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 49 * therefore they must be page-aligned. It is the responsibility of the linker 50 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 51 * refer to page-aligned addresses. 52 */ 53 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 54 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 55 #define BL31_END (unsigned long)(&__BL31_END__) 56 57 #if USE_COHERENT_MEM 58 /* 59 * The next 2 constants identify the extents of the coherent memory region. 60 * These addresses are used by the MMU setup code and therefore they must be 61 * page-aligned. It is the responsibility of the linker script to ensure that 62 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 63 * refer to page-aligned addresses. 64 */ 65 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 66 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 67 #endif 68 69 /* 70 * Placeholder variables for copying the arguments that have been passed to 71 * BL3-1 from BL2. 72 */ 73 static entry_point_info_t bl32_image_ep_info; 74 static entry_point_info_t bl33_image_ep_info; 75 76 77 /* Weak definitions may be overridden in specific ARM standard platform */ 78 #pragma weak bl31_early_platform_setup 79 #pragma weak bl31_platform_setup 80 #pragma weak bl31_plat_arch_setup 81 #pragma weak bl31_plat_get_next_image_ep_info 82 #pragma weak plat_get_syscnt_freq 83 84 85 /******************************************************************************* 86 * Return a pointer to the 'entry_point_info' structure of the next image for the 87 * security state specified. BL3-3 corresponds to the non-secure image type 88 * while BL3-2 corresponds to the secure image type. A NULL pointer is returned 89 * if the image does not exist. 90 ******************************************************************************/ 91 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 92 { 93 entry_point_info_t *next_image_info; 94 95 assert(sec_state_is_valid(type)); 96 next_image_info = (type == NON_SECURE) 97 ? &bl33_image_ep_info : &bl32_image_ep_info; 98 /* 99 * None of the images on the ARM development platforms can have 0x0 100 * as the entrypoint 101 */ 102 if (next_image_info->pc) 103 return next_image_info; 104 else 105 return NULL; 106 } 107 108 /******************************************************************************* 109 * Perform any BL3-1 early platform setup common to ARM standard platforms. 110 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 111 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 112 * done before the MMU is initialized so that the memory layout can be used 113 * while creating page tables. BL2 has flushed this information to memory, so 114 * we are guaranteed to pick up good data. 115 ******************************************************************************/ 116 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, 117 void *plat_params_from_bl2) 118 { 119 /* Initialize the console to provide early debug support */ 120 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 121 ARM_CONSOLE_BAUDRATE); 122 123 #if RESET_TO_BL31 124 /* There are no parameters from BL2 if BL3-1 is a reset vector */ 125 assert(from_bl2 == NULL); 126 assert(plat_params_from_bl2 == NULL); 127 128 /* Populate entry point information for BL3-2 and BL3-3 */ 129 SET_PARAM_HEAD(&bl32_image_ep_info, 130 PARAM_EP, 131 VERSION_1, 132 0); 133 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 134 bl32_image_ep_info.pc = BL32_BASE; 135 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 136 137 SET_PARAM_HEAD(&bl33_image_ep_info, 138 PARAM_EP, 139 VERSION_1, 140 0); 141 /* 142 * Tell BL3-1 where the non-trusted software image 143 * is located and the entry state information 144 */ 145 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 146 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 147 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 148 149 #else 150 /* 151 * Check params passed from BL2 should not be NULL, 152 */ 153 assert(from_bl2 != NULL); 154 assert(from_bl2->h.type == PARAM_BL31); 155 assert(from_bl2->h.version >= VERSION_1); 156 /* 157 * In debug builds, we pass a special value in 'plat_params_from_bl2' 158 * to verify platform parameters from BL2 to BL3-1. 159 * In release builds, it's not used. 160 */ 161 assert(((unsigned long long)plat_params_from_bl2) == 162 ARM_BL31_PLAT_PARAM_VAL); 163 164 /* 165 * Copy BL3-2 and BL3-3 entry point information. 166 * They are stored in Secure RAM, in BL2's address space. 167 */ 168 bl32_image_ep_info = *from_bl2->bl32_ep_info; 169 bl33_image_ep_info = *from_bl2->bl33_ep_info; 170 #endif 171 } 172 173 void bl31_early_platform_setup(bl31_params_t *from_bl2, 174 void *plat_params_from_bl2) 175 { 176 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); 177 178 /* 179 * Initialize CCI for this cluster during cold boot. 180 * No need for locks as no other CPU is active. 181 */ 182 arm_cci_init(); 183 184 /* 185 * Enable CCI coherency for the primary CPU's cluster. 186 * Earlier bootloader stages might already do this (e.g. Trusted 187 * Firmware's BL1 does it) but we can't assume so. There is no harm in 188 * executing this code twice anyway. 189 * Platform specific PSCI code will enable coherency for other 190 * clusters. 191 */ 192 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 193 } 194 195 /******************************************************************************* 196 * Perform any BL3-1 platform setup common to ARM standard platforms 197 ******************************************************************************/ 198 void arm_bl31_platform_setup(void) 199 { 200 unsigned int reg_val; 201 202 /* Initialize the gic cpu and distributor interfaces */ 203 plat_arm_gic_init(); 204 arm_gic_setup(); 205 206 #if RESET_TO_BL31 207 /* 208 * Do initial security configuration to allow DRAM/device access 209 * (if earlier BL has not already done so). 210 */ 211 plat_arm_security_setup(); 212 213 #endif /* RESET_TO_BL31 */ 214 215 /* Enable and initialize the System level generic timer */ 216 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 217 CNTCR_FCREQ(0) | CNTCR_EN); 218 219 /* Allow access to the System counter timer module */ 220 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 221 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 222 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 223 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 224 225 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 226 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 227 228 /* Initialize power controller before setting up topology */ 229 plat_arm_pwrc_setup(); 230 } 231 232 void bl31_platform_setup(void) 233 { 234 arm_bl31_platform_setup(); 235 } 236 237 /******************************************************************************* 238 * Perform the very early platform specific architectural setup here. At the 239 * moment this is only intializes the mmu in a quick and dirty way. 240 ******************************************************************************/ 241 void arm_bl31_plat_arch_setup(void) 242 { 243 arm_configure_mmu_el3(BL31_RO_BASE, 244 (BL31_END - BL31_RO_BASE), 245 BL31_RO_BASE, 246 BL31_RO_LIMIT 247 #if USE_COHERENT_MEM 248 , BL31_COHERENT_RAM_BASE, 249 BL31_COHERENT_RAM_LIMIT 250 #endif 251 ); 252 } 253 254 void bl31_plat_arch_setup(void) 255 { 256 arm_bl31_plat_arch_setup(); 257 } 258 259 uint64_t plat_get_syscnt_freq(void) 260 { 261 uint64_t counter_base_frequency; 262 263 /* Read the frequency from Frequency modes table */ 264 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 265 266 /* The first entry of the frequency modes table must not be 0 */ 267 if (counter_base_frequency == 0) 268 panic(); 269 270 return counter_base_frequency; 271 } 272