1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 /* 23 * Placeholder variables for copying the arguments that have been passed to 24 * BL31 from BL2. 25 */ 26 static entry_point_info_t bl32_image_ep_info; 27 static entry_point_info_t bl33_image_ep_info; 28 29 #if !RESET_TO_BL31 30 /* 31 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 32 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 33 */ 34 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 35 #endif 36 37 /* Weak definitions may be overridden in specific ARM standard platform */ 38 #pragma weak bl31_early_platform_setup2 39 #pragma weak bl31_platform_setup 40 #pragma weak bl31_plat_arch_setup 41 #pragma weak bl31_plat_get_next_image_ep_info 42 43 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 44 BL31_START, \ 45 BL31_END - BL31_START, \ 46 MT_MEMORY | MT_RW | MT_SECURE) 47 #if RECLAIM_INIT_CODE 48 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 49 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 50 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 51 52 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 53 ~(PAGE_SIZE - 1)) 54 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 55 ~(PAGE_SIZE - 1)) 56 57 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 58 BL_INIT_CODE_BASE, \ 59 BL_INIT_CODE_END \ 60 - BL_INIT_CODE_BASE, \ 61 MT_CODE | MT_SECURE) 62 #endif 63 64 #if SEPARATE_NOBITS_REGION 65 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 66 BL31_NOBITS_BASE, \ 67 BL31_NOBITS_LIMIT \ 68 - BL31_NOBITS_BASE, \ 69 MT_MEMORY | MT_RW | MT_SECURE) 70 71 #endif 72 /******************************************************************************* 73 * Return a pointer to the 'entry_point_info' structure of the next image for the 74 * security state specified. BL33 corresponds to the non-secure image type 75 * while BL32 corresponds to the secure image type. A NULL pointer is returned 76 * if the image does not exist. 77 ******************************************************************************/ 78 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 79 { 80 entry_point_info_t *next_image_info; 81 82 assert(sec_state_is_valid(type)); 83 next_image_info = (type == NON_SECURE) 84 ? &bl33_image_ep_info : &bl32_image_ep_info; 85 /* 86 * None of the images on the ARM development platforms can have 0x0 87 * as the entrypoint 88 */ 89 if (next_image_info->pc) 90 return next_image_info; 91 else 92 return NULL; 93 } 94 95 /******************************************************************************* 96 * Perform any BL31 early platform setup common to ARM standard platforms. 97 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 98 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 99 * done before the MMU is initialized so that the memory layout can be used 100 * while creating page tables. BL2 has flushed this information to memory, so 101 * we are guaranteed to pick up good data. 102 ******************************************************************************/ 103 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 104 uintptr_t hw_config, void *plat_params_from_bl2) 105 { 106 /* Initialize the console to provide early debug support */ 107 arm_console_boot_init(); 108 109 #if RESET_TO_BL31 110 /* There are no parameters from BL2 if BL31 is a reset vector */ 111 assert(from_bl2 == NULL); 112 assert(plat_params_from_bl2 == NULL); 113 114 # ifdef BL32_BASE 115 /* Populate entry point information for BL32 */ 116 SET_PARAM_HEAD(&bl32_image_ep_info, 117 PARAM_EP, 118 VERSION_1, 119 0); 120 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 121 bl32_image_ep_info.pc = BL32_BASE; 122 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 123 124 #if defined(SPD_spmd) 125 /* SPM (hafnium in secure world) expects SPM Core manifest base address 126 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 127 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 128 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 129 * keep it in the last page. 130 */ 131 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 132 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 133 #endif 134 135 # endif /* BL32_BASE */ 136 137 /* Populate entry point information for BL33 */ 138 SET_PARAM_HEAD(&bl33_image_ep_info, 139 PARAM_EP, 140 VERSION_1, 141 0); 142 /* 143 * Tell BL31 where the non-trusted software image 144 * is located and the entry state information 145 */ 146 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 147 148 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 149 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 150 151 #else /* RESET_TO_BL31 */ 152 153 /* 154 * In debug builds, we pass a special value in 'plat_params_from_bl2' 155 * to verify platform parameters from BL2 to BL31. 156 * In release builds, it's not used. 157 */ 158 assert(((unsigned long long)plat_params_from_bl2) == 159 ARM_BL31_PLAT_PARAM_VAL); 160 161 /* 162 * Check params passed from BL2 should not be NULL, 163 */ 164 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 165 assert(params_from_bl2 != NULL); 166 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 167 assert(params_from_bl2->h.version >= VERSION_2); 168 169 bl_params_node_t *bl_params = params_from_bl2->head; 170 171 /* 172 * Copy BL33 and BL32 (if present), entry point information. 173 * They are stored in Secure RAM, in BL2's address space. 174 */ 175 while (bl_params != NULL) { 176 if (bl_params->image_id == BL32_IMAGE_ID) 177 bl32_image_ep_info = *bl_params->ep_info; 178 179 if (bl_params->image_id == BL33_IMAGE_ID) 180 bl33_image_ep_info = *bl_params->ep_info; 181 182 bl_params = bl_params->next_params_info; 183 } 184 185 if (bl33_image_ep_info.pc == 0U) 186 panic(); 187 #endif /* RESET_TO_BL31 */ 188 189 # if ARM_LINUX_KERNEL_AS_BL33 190 /* 191 * According to the file ``Documentation/arm64/booting.txt`` of the 192 * Linux kernel tree, Linux expects the physical address of the device 193 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 194 * must be 0. 195 */ 196 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 197 bl33_image_ep_info.args.arg1 = 0U; 198 bl33_image_ep_info.args.arg2 = 0U; 199 bl33_image_ep_info.args.arg3 = 0U; 200 # endif 201 202 #if defined(SPD_spmd) 203 /* 204 * Hafnium in normal world expects its manifest address in x0, In CI 205 * configuration manifest is preloaded at 0x80000000(start of DRAM). 206 */ 207 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 208 #endif 209 } 210 211 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 212 u_register_t arg2, u_register_t arg3) 213 { 214 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 215 216 /* 217 * Initialize Interconnect for this cluster during cold boot. 218 * No need for locks as no other CPU is active. 219 */ 220 plat_arm_interconnect_init(); 221 222 /* 223 * Enable Interconnect coherency for the primary CPU's cluster. 224 * Earlier bootloader stages might already do this (e.g. Trusted 225 * Firmware's BL1 does it) but we can't assume so. There is no harm in 226 * executing this code twice anyway. 227 * Platform specific PSCI code will enable coherency for other 228 * clusters. 229 */ 230 plat_arm_interconnect_enter_coherency(); 231 } 232 233 /******************************************************************************* 234 * Perform any BL31 platform setup common to ARM standard platforms 235 ******************************************************************************/ 236 void arm_bl31_platform_setup(void) 237 { 238 /* Initialize the GIC driver, cpu and distributor interfaces */ 239 plat_arm_gic_driver_init(); 240 plat_arm_gic_init(); 241 242 #if RESET_TO_BL31 243 /* 244 * Do initial security configuration to allow DRAM/device access 245 * (if earlier BL has not already done so). 246 */ 247 plat_arm_security_setup(); 248 249 #if defined(PLAT_ARM_MEM_PROT_ADDR) 250 arm_nor_psci_do_dyn_mem_protect(); 251 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 252 253 #endif /* RESET_TO_BL31 */ 254 255 /* Enable and initialize the System level generic timer */ 256 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 257 CNTCR_FCREQ(0U) | CNTCR_EN); 258 259 /* Allow access to the System counter timer module */ 260 arm_configure_sys_timer(); 261 262 /* Initialize power controller before setting up topology */ 263 plat_arm_pwrc_setup(); 264 265 #if RAS_EXTENSION 266 ras_init(); 267 #endif 268 269 #if USE_DEBUGFS 270 debugfs_init(); 271 #endif /* USE_DEBUGFS */ 272 } 273 274 /******************************************************************************* 275 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 276 * standard platforms 277 * Perform BL31 platform setup 278 ******************************************************************************/ 279 void arm_bl31_plat_runtime_setup(void) 280 { 281 console_switch_state(CONSOLE_FLAG_RUNTIME); 282 283 /* Initialize the runtime console */ 284 arm_console_runtime_init(); 285 286 #if RECLAIM_INIT_CODE 287 arm_free_init_memory(); 288 #endif 289 290 #if PLAT_RO_XLAT_TABLES 291 arm_xlat_make_tables_readonly(); 292 #endif 293 } 294 295 #if RECLAIM_INIT_CODE 296 /* 297 * Make memory for image boot time code RW to reclaim it as stack for the 298 * secondary cores, or RO where it cannot be reclaimed: 299 * 300 * |-------- INIT SECTION --------| 301 * ----------------------------------------- 302 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 303 * | STACK | STACK | STACK | SPACE | 304 * ----------------------------------------- 305 * <-------------------> <------> 306 * MAKE RW AND XN MAKE 307 * FOR STACKS RO AND XN 308 */ 309 void arm_free_init_memory(void) 310 { 311 int ret = 0; 312 313 if (BL_STACKS_END < BL_INIT_CODE_END) { 314 /* Reclaim some of the init section as stack if possible. */ 315 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 316 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 317 BL_STACKS_END - BL_INIT_CODE_BASE, 318 MT_RW_DATA); 319 } 320 /* Make the rest of the init section read-only. */ 321 ret |= xlat_change_mem_attributes(BL_STACKS_END, 322 BL_INIT_CODE_END - BL_STACKS_END, 323 MT_RO_DATA); 324 } else { 325 /* The stacks cover the init section, so reclaim it all. */ 326 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 327 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 328 MT_RW_DATA); 329 } 330 331 if (ret != 0) { 332 ERROR("Could not reclaim initialization code"); 333 panic(); 334 } 335 } 336 #endif 337 338 void __init bl31_platform_setup(void) 339 { 340 arm_bl31_platform_setup(); 341 } 342 343 void bl31_plat_runtime_setup(void) 344 { 345 arm_bl31_plat_runtime_setup(); 346 } 347 348 /******************************************************************************* 349 * Perform the very early platform specific architectural setup shared between 350 * ARM standard platforms. This only does basic initialization. Later 351 * architectural setup (bl31_arch_setup()) does not do anything platform 352 * specific. 353 ******************************************************************************/ 354 void __init arm_bl31_plat_arch_setup(void) 355 { 356 const mmap_region_t bl_regions[] = { 357 MAP_BL31_TOTAL, 358 #if RECLAIM_INIT_CODE 359 MAP_BL_INIT_CODE, 360 #endif 361 #if SEPARATE_NOBITS_REGION 362 MAP_BL31_NOBITS, 363 #endif 364 ARM_MAP_BL_RO, 365 #if USE_ROMLIB 366 ARM_MAP_ROMLIB_CODE, 367 ARM_MAP_ROMLIB_DATA, 368 #endif 369 #if USE_COHERENT_MEM 370 ARM_MAP_BL_COHERENT_RAM, 371 #endif 372 {0} 373 }; 374 375 setup_page_tables(bl_regions, plat_arm_get_mmap()); 376 377 enable_mmu_el3(0); 378 379 arm_setup_romlib(); 380 } 381 382 void __init bl31_plat_arch_setup(void) 383 { 384 arm_bl31_plat_arch_setup(); 385 } 386