1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <arm_def.h> 34 #include <assert.h> 35 #include <bl_common.h> 36 #include <cci.h> 37 #include <console.h> 38 #include <debug.h> 39 #include <mmio.h> 40 #include <plat_arm.h> 41 #include <platform.h> 42 43 44 /* 45 * The next 3 constants identify the extents of the code, RO data region and the 46 * limit of the BL31 image. These addresses are used by the MMU setup code and 47 * therefore they must be page-aligned. It is the responsibility of the linker 48 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 49 * refer to page-aligned addresses. 50 */ 51 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 52 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 53 #define BL31_END (unsigned long)(&__BL31_END__) 54 55 #if USE_COHERENT_MEM 56 /* 57 * The next 2 constants identify the extents of the coherent memory region. 58 * These addresses are used by the MMU setup code and therefore they must be 59 * page-aligned. It is the responsibility of the linker script to ensure that 60 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 61 * refer to page-aligned addresses. 62 */ 63 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 64 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 65 #endif 66 67 /* 68 * Placeholder variables for copying the arguments that have been passed to 69 * BL31 from BL2. 70 */ 71 static entry_point_info_t bl32_image_ep_info; 72 static entry_point_info_t bl33_image_ep_info; 73 74 75 /* Weak definitions may be overridden in specific ARM standard platform */ 76 #pragma weak bl31_early_platform_setup 77 #pragma weak bl31_platform_setup 78 #pragma weak bl31_plat_arch_setup 79 #pragma weak bl31_plat_get_next_image_ep_info 80 #pragma weak plat_get_syscnt_freq 81 82 83 /******************************************************************************* 84 * Return a pointer to the 'entry_point_info' structure of the next image for the 85 * security state specified. BL33 corresponds to the non-secure image type 86 * while BL32 corresponds to the secure image type. A NULL pointer is returned 87 * if the image does not exist. 88 ******************************************************************************/ 89 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 90 { 91 entry_point_info_t *next_image_info; 92 93 assert(sec_state_is_valid(type)); 94 next_image_info = (type == NON_SECURE) 95 ? &bl33_image_ep_info : &bl32_image_ep_info; 96 /* 97 * None of the images on the ARM development platforms can have 0x0 98 * as the entrypoint 99 */ 100 if (next_image_info->pc) 101 return next_image_info; 102 else 103 return NULL; 104 } 105 106 /******************************************************************************* 107 * Perform any BL31 early platform setup common to ARM standard platforms. 108 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 109 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 110 * done before the MMU is initialized so that the memory layout can be used 111 * while creating page tables. BL2 has flushed this information to memory, so 112 * we are guaranteed to pick up good data. 113 ******************************************************************************/ 114 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, 115 void *plat_params_from_bl2) 116 { 117 /* Initialize the console to provide early debug support */ 118 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 119 ARM_CONSOLE_BAUDRATE); 120 121 #if RESET_TO_BL31 122 /* There are no parameters from BL2 if BL31 is a reset vector */ 123 assert(from_bl2 == NULL); 124 assert(plat_params_from_bl2 == NULL); 125 126 #ifdef BL32_BASE 127 /* Populate entry point information for BL32 */ 128 SET_PARAM_HEAD(&bl32_image_ep_info, 129 PARAM_EP, 130 VERSION_1, 131 0); 132 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 133 bl32_image_ep_info.pc = BL32_BASE; 134 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 135 #endif /* BL32_BASE */ 136 137 /* Populate entry point information for BL33 */ 138 SET_PARAM_HEAD(&bl33_image_ep_info, 139 PARAM_EP, 140 VERSION_1, 141 0); 142 /* 143 * Tell BL31 where the non-trusted software image 144 * is located and the entry state information 145 */ 146 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 147 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 148 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 149 150 #else 151 /* 152 * Check params passed from BL2 should not be NULL, 153 */ 154 assert(from_bl2 != NULL); 155 assert(from_bl2->h.type == PARAM_BL31); 156 assert(from_bl2->h.version >= VERSION_1); 157 /* 158 * In debug builds, we pass a special value in 'plat_params_from_bl2' 159 * to verify platform parameters from BL2 to BL31. 160 * In release builds, it's not used. 161 */ 162 assert(((unsigned long long)plat_params_from_bl2) == 163 ARM_BL31_PLAT_PARAM_VAL); 164 165 /* 166 * Copy BL32 (if populated by BL2) and BL33 entry point information. 167 * They are stored in Secure RAM, in BL2's address space. 168 */ 169 if (from_bl2->bl32_ep_info) 170 bl32_image_ep_info = *from_bl2->bl32_ep_info; 171 bl33_image_ep_info = *from_bl2->bl33_ep_info; 172 #endif 173 } 174 175 void bl31_early_platform_setup(bl31_params_t *from_bl2, 176 void *plat_params_from_bl2) 177 { 178 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); 179 180 /* 181 * Initialize CCI for this cluster during cold boot. 182 * No need for locks as no other CPU is active. 183 */ 184 arm_cci_init(); 185 186 /* 187 * Enable CCI coherency for the primary CPU's cluster. 188 * Earlier bootloader stages might already do this (e.g. Trusted 189 * Firmware's BL1 does it) but we can't assume so. There is no harm in 190 * executing this code twice anyway. 191 * Platform specific PSCI code will enable coherency for other 192 * clusters. 193 */ 194 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 195 } 196 197 /******************************************************************************* 198 * Perform any BL31 platform setup common to ARM standard platforms 199 ******************************************************************************/ 200 void arm_bl31_platform_setup(void) 201 { 202 /* Initialize the GIC driver, cpu and distributor interfaces */ 203 plat_arm_gic_driver_init(); 204 plat_arm_gic_init(); 205 206 #if RESET_TO_BL31 207 /* 208 * Do initial security configuration to allow DRAM/device access 209 * (if earlier BL has not already done so). 210 */ 211 plat_arm_security_setup(); 212 213 #endif /* RESET_TO_BL31 */ 214 215 /* Enable and initialize the System level generic timer */ 216 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 217 CNTCR_FCREQ(0) | CNTCR_EN); 218 219 /* Allow access to the System counter timer module */ 220 arm_configure_sys_timer(); 221 222 /* Initialize power controller before setting up topology */ 223 plat_arm_pwrc_setup(); 224 } 225 226 /******************************************************************************* 227 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 228 * standard platforms 229 ******************************************************************************/ 230 void arm_bl31_plat_runtime_setup(void) 231 { 232 /* Initialize the runtime console */ 233 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, 234 ARM_CONSOLE_BAUDRATE); 235 } 236 237 void bl31_platform_setup(void) 238 { 239 arm_bl31_platform_setup(); 240 } 241 242 void bl31_plat_runtime_setup(void) 243 { 244 arm_bl31_plat_runtime_setup(); 245 } 246 247 /******************************************************************************* 248 * Perform the very early platform specific architectural setup here. At the 249 * moment this is only intializes the mmu in a quick and dirty way. 250 ******************************************************************************/ 251 void arm_bl31_plat_arch_setup(void) 252 { 253 arm_configure_mmu_el3(BL31_RO_BASE, 254 (BL31_END - BL31_RO_BASE), 255 BL31_RO_BASE, 256 BL31_RO_LIMIT 257 #if USE_COHERENT_MEM 258 , BL31_COHERENT_RAM_BASE, 259 BL31_COHERENT_RAM_LIMIT 260 #endif 261 ); 262 } 263 264 void bl31_plat_arch_setup(void) 265 { 266 arm_bl31_plat_arch_setup(); 267 } 268 269 uint64_t plat_get_syscnt_freq(void) 270 { 271 uint64_t counter_base_frequency; 272 273 /* Read the frequency from Frequency modes table */ 274 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 275 276 /* The first entry of the frequency modes table must not be 0 */ 277 if (counter_base_frequency == 0) 278 panic(); 279 280 return counter_base_frequency; 281 } 282