1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 /* 23 * Placeholder variables for copying the arguments that have been passed to 24 * BL31 from BL2. 25 */ 26 static entry_point_info_t bl32_image_ep_info; 27 static entry_point_info_t bl33_image_ep_info; 28 29 #if !RESET_TO_BL31 30 /* 31 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 32 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 33 */ 34 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 35 #endif 36 37 /* Weak definitions may be overridden in specific ARM standard platform */ 38 #pragma weak bl31_early_platform_setup2 39 #pragma weak bl31_platform_setup 40 #pragma weak bl31_plat_arch_setup 41 #pragma weak bl31_plat_get_next_image_ep_info 42 43 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 44 BL31_START, \ 45 BL31_END - BL31_START, \ 46 MT_MEMORY | MT_RW | MT_SECURE) 47 #if RECLAIM_INIT_CODE 48 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 49 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 50 51 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 52 ~(PAGE_SIZE - 1)) 53 54 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 55 BL_INIT_CODE_BASE, \ 56 BL_INIT_CODE_END \ 57 - BL_INIT_CODE_BASE, \ 58 MT_CODE | MT_SECURE) 59 #endif 60 61 #if SEPARATE_NOBITS_REGION 62 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 63 BL31_NOBITS_BASE, \ 64 BL31_NOBITS_LIMIT \ 65 - BL31_NOBITS_BASE, \ 66 MT_MEMORY | MT_RW | MT_SECURE) 67 68 #endif 69 /******************************************************************************* 70 * Return a pointer to the 'entry_point_info' structure of the next image for the 71 * security state specified. BL33 corresponds to the non-secure image type 72 * while BL32 corresponds to the secure image type. A NULL pointer is returned 73 * if the image does not exist. 74 ******************************************************************************/ 75 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 76 { 77 entry_point_info_t *next_image_info; 78 79 assert(sec_state_is_valid(type)); 80 next_image_info = (type == NON_SECURE) 81 ? &bl33_image_ep_info : &bl32_image_ep_info; 82 /* 83 * None of the images on the ARM development platforms can have 0x0 84 * as the entrypoint 85 */ 86 if (next_image_info->pc) 87 return next_image_info; 88 else 89 return NULL; 90 } 91 92 /******************************************************************************* 93 * Perform any BL31 early platform setup common to ARM standard platforms. 94 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 95 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 96 * done before the MMU is initialized so that the memory layout can be used 97 * while creating page tables. BL2 has flushed this information to memory, so 98 * we are guaranteed to pick up good data. 99 ******************************************************************************/ 100 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 101 uintptr_t hw_config, void *plat_params_from_bl2) 102 { 103 /* Initialize the console to provide early debug support */ 104 arm_console_boot_init(); 105 106 #if RESET_TO_BL31 107 /* There are no parameters from BL2 if BL31 is a reset vector */ 108 assert(from_bl2 == NULL); 109 assert(plat_params_from_bl2 == NULL); 110 111 # ifdef BL32_BASE 112 /* Populate entry point information for BL32 */ 113 SET_PARAM_HEAD(&bl32_image_ep_info, 114 PARAM_EP, 115 VERSION_1, 116 0); 117 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 118 bl32_image_ep_info.pc = BL32_BASE; 119 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 120 121 #if defined(SPD_spmd) 122 /* SPM (hafnium in secure world) expects SPM Core manifest base address 123 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 124 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 125 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 126 * keep it in the last page. 127 */ 128 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 129 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 130 #endif 131 132 # endif /* BL32_BASE */ 133 134 /* Populate entry point information for BL33 */ 135 SET_PARAM_HEAD(&bl33_image_ep_info, 136 PARAM_EP, 137 VERSION_1, 138 0); 139 /* 140 * Tell BL31 where the non-trusted software image 141 * is located and the entry state information 142 */ 143 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 144 145 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 146 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 147 148 #if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33) 149 /* 150 * Hafnium in normal world expects its manifest address in x0, which 151 * is loaded at base of DRAM. 152 */ 153 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 154 #endif 155 156 # if ARM_LINUX_KERNEL_AS_BL33 157 /* 158 * According to the file ``Documentation/arm64/booting.txt`` of the 159 * Linux kernel tree, Linux expects the physical address of the device 160 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 161 * must be 0. 162 */ 163 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 164 bl33_image_ep_info.args.arg1 = 0U; 165 bl33_image_ep_info.args.arg2 = 0U; 166 bl33_image_ep_info.args.arg3 = 0U; 167 # endif 168 169 #else /* RESET_TO_BL31 */ 170 171 /* 172 * In debug builds, we pass a special value in 'plat_params_from_bl2' 173 * to verify platform parameters from BL2 to BL31. 174 * In release builds, it's not used. 175 */ 176 assert(((unsigned long long)plat_params_from_bl2) == 177 ARM_BL31_PLAT_PARAM_VAL); 178 179 /* 180 * Check params passed from BL2 should not be NULL, 181 */ 182 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 183 assert(params_from_bl2 != NULL); 184 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 185 assert(params_from_bl2->h.version >= VERSION_2); 186 187 bl_params_node_t *bl_params = params_from_bl2->head; 188 189 /* 190 * Copy BL33 and BL32 (if present), entry point information. 191 * They are stored in Secure RAM, in BL2's address space. 192 */ 193 while (bl_params != NULL) { 194 if (bl_params->image_id == BL32_IMAGE_ID) 195 bl32_image_ep_info = *bl_params->ep_info; 196 197 if (bl_params->image_id == BL33_IMAGE_ID) 198 bl33_image_ep_info = *bl_params->ep_info; 199 200 bl_params = bl_params->next_params_info; 201 } 202 203 if (bl33_image_ep_info.pc == 0U) 204 panic(); 205 #endif /* RESET_TO_BL31 */ 206 } 207 208 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 209 u_register_t arg2, u_register_t arg3) 210 { 211 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 212 213 /* 214 * Initialize Interconnect for this cluster during cold boot. 215 * No need for locks as no other CPU is active. 216 */ 217 plat_arm_interconnect_init(); 218 219 /* 220 * Enable Interconnect coherency for the primary CPU's cluster. 221 * Earlier bootloader stages might already do this (e.g. Trusted 222 * Firmware's BL1 does it) but we can't assume so. There is no harm in 223 * executing this code twice anyway. 224 * Platform specific PSCI code will enable coherency for other 225 * clusters. 226 */ 227 plat_arm_interconnect_enter_coherency(); 228 } 229 230 /******************************************************************************* 231 * Perform any BL31 platform setup common to ARM standard platforms 232 ******************************************************************************/ 233 void arm_bl31_platform_setup(void) 234 { 235 /* Initialize the GIC driver, cpu and distributor interfaces */ 236 plat_arm_gic_driver_init(); 237 plat_arm_gic_init(); 238 239 #if RESET_TO_BL31 240 /* 241 * Do initial security configuration to allow DRAM/device access 242 * (if earlier BL has not already done so). 243 */ 244 plat_arm_security_setup(); 245 246 #if defined(PLAT_ARM_MEM_PROT_ADDR) 247 arm_nor_psci_do_dyn_mem_protect(); 248 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 249 250 #endif /* RESET_TO_BL31 */ 251 252 /* Enable and initialize the System level generic timer */ 253 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 254 CNTCR_FCREQ(0U) | CNTCR_EN); 255 256 /* Allow access to the System counter timer module */ 257 arm_configure_sys_timer(); 258 259 /* Initialize power controller before setting up topology */ 260 plat_arm_pwrc_setup(); 261 262 #if RAS_EXTENSION 263 ras_init(); 264 #endif 265 266 #if USE_DEBUGFS 267 debugfs_init(); 268 #endif /* USE_DEBUGFS */ 269 } 270 271 /******************************************************************************* 272 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 273 * standard platforms 274 * Perform BL31 platform setup 275 ******************************************************************************/ 276 void arm_bl31_plat_runtime_setup(void) 277 { 278 console_switch_state(CONSOLE_FLAG_RUNTIME); 279 280 /* Initialize the runtime console */ 281 arm_console_runtime_init(); 282 283 #if RECLAIM_INIT_CODE 284 arm_free_init_memory(); 285 #endif 286 287 #if PLAT_RO_XLAT_TABLES 288 arm_xlat_make_tables_readonly(); 289 #endif 290 } 291 292 #if RECLAIM_INIT_CODE 293 /* 294 * Zero out and make RW memory used to store image boot time code so it can 295 * be reclaimed during runtime 296 */ 297 void arm_free_init_memory(void) 298 { 299 int ret = xlat_change_mem_attributes(BL_INIT_CODE_BASE, 300 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 301 MT_RW_DATA); 302 303 if (ret != 0) { 304 ERROR("Could not reclaim initialization code"); 305 panic(); 306 } 307 } 308 #endif 309 310 void __init bl31_platform_setup(void) 311 { 312 arm_bl31_platform_setup(); 313 } 314 315 void bl31_plat_runtime_setup(void) 316 { 317 arm_bl31_plat_runtime_setup(); 318 } 319 320 /******************************************************************************* 321 * Perform the very early platform specific architectural setup shared between 322 * ARM standard platforms. This only does basic initialization. Later 323 * architectural setup (bl31_arch_setup()) does not do anything platform 324 * specific. 325 ******************************************************************************/ 326 void __init arm_bl31_plat_arch_setup(void) 327 { 328 const mmap_region_t bl_regions[] = { 329 MAP_BL31_TOTAL, 330 #if RECLAIM_INIT_CODE 331 MAP_BL_INIT_CODE, 332 #endif 333 #if SEPARATE_NOBITS_REGION 334 MAP_BL31_NOBITS, 335 #endif 336 ARM_MAP_BL_RO, 337 #if USE_ROMLIB 338 ARM_MAP_ROMLIB_CODE, 339 ARM_MAP_ROMLIB_DATA, 340 #endif 341 #if USE_COHERENT_MEM 342 ARM_MAP_BL_COHERENT_RAM, 343 #endif 344 {0} 345 }; 346 347 setup_page_tables(bl_regions, plat_arm_get_mmap()); 348 349 enable_mmu_el3(0); 350 351 arm_setup_romlib(); 352 } 353 354 void __init bl31_plat_arch_setup(void) 355 { 356 arm_bl31_plat_arch_setup(); 357 } 358