1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <platform.h> 17 #include <ras.h> 18 19 #define BL31_END (uintptr_t)(&__BL31_END__) 20 21 /* 22 * Placeholder variables for copying the arguments that have been passed to 23 * BL31 from BL2. 24 */ 25 static entry_point_info_t bl32_image_ep_info; 26 static entry_point_info_t bl33_image_ep_info; 27 28 /* 29 * Check that BL31_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 30 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 31 */ 32 CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 33 34 /* Weak definitions may be overridden in specific ARM standard platform */ 35 #pragma weak bl31_early_platform_setup2 36 #pragma weak bl31_platform_setup 37 #pragma weak bl31_plat_arch_setup 38 #pragma weak bl31_plat_get_next_image_ep_info 39 40 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 41 BL31_BASE, \ 42 BL31_END - BL31_BASE, \ 43 MT_MEMORY | MT_RW | MT_SECURE) 44 45 /******************************************************************************* 46 * Return a pointer to the 'entry_point_info' structure of the next image for the 47 * security state specified. BL33 corresponds to the non-secure image type 48 * while BL32 corresponds to the secure image type. A NULL pointer is returned 49 * if the image does not exist. 50 ******************************************************************************/ 51 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 52 { 53 entry_point_info_t *next_image_info; 54 55 assert(sec_state_is_valid(type)); 56 next_image_info = (type == NON_SECURE) 57 ? &bl33_image_ep_info : &bl32_image_ep_info; 58 /* 59 * None of the images on the ARM development platforms can have 0x0 60 * as the entrypoint 61 */ 62 if (next_image_info->pc) 63 return next_image_info; 64 else 65 return NULL; 66 } 67 68 /******************************************************************************* 69 * Perform any BL31 early platform setup common to ARM standard platforms. 70 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 71 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 72 * done before the MMU is initialized so that the memory layout can be used 73 * while creating page tables. BL2 has flushed this information to memory, so 74 * we are guaranteed to pick up good data. 75 ******************************************************************************/ 76 #if LOAD_IMAGE_V2 77 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 78 uintptr_t hw_config, void *plat_params_from_bl2) 79 #else 80 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config, 81 uintptr_t hw_config, void *plat_params_from_bl2) 82 #endif 83 { 84 /* Initialize the console to provide early debug support */ 85 arm_console_boot_init(); 86 87 #if RESET_TO_BL31 88 /* There are no parameters from BL2 if BL31 is a reset vector */ 89 assert(from_bl2 == NULL); 90 assert(plat_params_from_bl2 == NULL); 91 92 # ifdef BL32_BASE 93 /* Populate entry point information for BL32 */ 94 SET_PARAM_HEAD(&bl32_image_ep_info, 95 PARAM_EP, 96 VERSION_1, 97 0); 98 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 99 bl32_image_ep_info.pc = BL32_BASE; 100 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 101 # endif /* BL32_BASE */ 102 103 /* Populate entry point information for BL33 */ 104 SET_PARAM_HEAD(&bl33_image_ep_info, 105 PARAM_EP, 106 VERSION_1, 107 0); 108 /* 109 * Tell BL31 where the non-trusted software image 110 * is located and the entry state information 111 */ 112 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 113 114 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 115 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 116 117 # if ARM_LINUX_KERNEL_AS_BL33 118 /* 119 * According to the file ``Documentation/arm64/booting.txt`` of the 120 * Linux kernel tree, Linux expects the physical address of the device 121 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 122 * must be 0. 123 */ 124 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 125 bl33_image_ep_info.args.arg1 = 0U; 126 bl33_image_ep_info.args.arg2 = 0U; 127 bl33_image_ep_info.args.arg3 = 0U; 128 # endif 129 130 #else /* RESET_TO_BL31 */ 131 132 /* 133 * In debug builds, we pass a special value in 'plat_params_from_bl2' 134 * to verify platform parameters from BL2 to BL31. 135 * In release builds, it's not used. 136 */ 137 assert(((unsigned long long)plat_params_from_bl2) == 138 ARM_BL31_PLAT_PARAM_VAL); 139 140 # if LOAD_IMAGE_V2 141 /* 142 * Check params passed from BL2 should not be NULL, 143 */ 144 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 145 assert(params_from_bl2 != NULL); 146 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 147 assert(params_from_bl2->h.version >= VERSION_2); 148 149 bl_params_node_t *bl_params = params_from_bl2->head; 150 151 /* 152 * Copy BL33 and BL32 (if present), entry point information. 153 * They are stored in Secure RAM, in BL2's address space. 154 */ 155 while (bl_params) { 156 if (bl_params->image_id == BL32_IMAGE_ID) 157 bl32_image_ep_info = *bl_params->ep_info; 158 159 if (bl_params->image_id == BL33_IMAGE_ID) 160 bl33_image_ep_info = *bl_params->ep_info; 161 162 bl_params = bl_params->next_params_info; 163 } 164 165 if (bl33_image_ep_info.pc == 0) 166 panic(); 167 168 # else /* LOAD_IMAGE_V2 */ 169 170 /* 171 * Check params passed from BL2 should not be NULL, 172 */ 173 assert(from_bl2 != NULL); 174 assert(from_bl2->h.type == PARAM_BL31); 175 assert(from_bl2->h.version >= VERSION_1); 176 177 /* Dynamic Config is not supported for LOAD_IMAGE_V1 */ 178 assert(soc_fw_config == 0); 179 assert(hw_config == 0); 180 181 /* 182 * Copy BL32 (if populated by BL2) and BL33 entry point information. 183 * They are stored in Secure RAM, in BL2's address space. 184 */ 185 if (from_bl2->bl32_ep_info) 186 bl32_image_ep_info = *from_bl2->bl32_ep_info; 187 bl33_image_ep_info = *from_bl2->bl33_ep_info; 188 189 # endif /* LOAD_IMAGE_V2 */ 190 #endif /* RESET_TO_BL31 */ 191 } 192 193 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 194 u_register_t arg2, u_register_t arg3) 195 { 196 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 197 198 /* 199 * Initialize Interconnect for this cluster during cold boot. 200 * No need for locks as no other CPU is active. 201 */ 202 plat_arm_interconnect_init(); 203 204 /* 205 * Enable Interconnect coherency for the primary CPU's cluster. 206 * Earlier bootloader stages might already do this (e.g. Trusted 207 * Firmware's BL1 does it) but we can't assume so. There is no harm in 208 * executing this code twice anyway. 209 * Platform specific PSCI code will enable coherency for other 210 * clusters. 211 */ 212 plat_arm_interconnect_enter_coherency(); 213 } 214 215 /******************************************************************************* 216 * Perform any BL31 platform setup common to ARM standard platforms 217 ******************************************************************************/ 218 void arm_bl31_platform_setup(void) 219 { 220 /* Initialize the GIC driver, cpu and distributor interfaces */ 221 plat_arm_gic_driver_init(); 222 plat_arm_gic_init(); 223 224 #if RESET_TO_BL31 225 /* 226 * Do initial security configuration to allow DRAM/device access 227 * (if earlier BL has not already done so). 228 */ 229 plat_arm_security_setup(); 230 231 #if defined(PLAT_ARM_MEM_PROT_ADDR) 232 arm_nor_psci_do_dyn_mem_protect(); 233 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 234 235 #endif /* RESET_TO_BL31 */ 236 237 /* Enable and initialize the System level generic timer */ 238 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 239 CNTCR_FCREQ(0) | CNTCR_EN); 240 241 /* Allow access to the System counter timer module */ 242 arm_configure_sys_timer(); 243 244 /* Initialize power controller before setting up topology */ 245 plat_arm_pwrc_setup(); 246 247 #if RAS_EXTENSION 248 ras_init(); 249 #endif 250 } 251 252 /******************************************************************************* 253 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 254 * standard platforms 255 * Perform BL31 platform setup 256 ******************************************************************************/ 257 void arm_bl31_plat_runtime_setup(void) 258 { 259 #if MULTI_CONSOLE_API 260 console_switch_state(CONSOLE_FLAG_RUNTIME); 261 #else 262 console_uninit(); 263 #endif 264 265 /* Initialize the runtime console */ 266 arm_console_runtime_init(); 267 } 268 269 void bl31_platform_setup(void) 270 { 271 arm_bl31_platform_setup(); 272 } 273 274 void bl31_plat_runtime_setup(void) 275 { 276 arm_bl31_plat_runtime_setup(); 277 } 278 279 /******************************************************************************* 280 * Perform the very early platform specific architectural setup shared between 281 * ARM standard platforms. This only does basic initialization. Later 282 * architectural setup (bl31_arch_setup()) does not do anything platform 283 * specific. 284 ******************************************************************************/ 285 void arm_bl31_plat_arch_setup(void) 286 { 287 288 #define ARM_MAP_BL_ROMLIB MAP_REGION_FLAT( \ 289 BL31_BASE, \ 290 BL31_END - BL31_BASE, \ 291 MT_MEMORY | MT_RW | MT_SECURE) 292 293 const mmap_region_t bl_regions[] = { 294 MAP_BL31_TOTAL, 295 ARM_MAP_BL_RO, 296 #if USE_ROMLIB 297 ARM_MAP_ROMLIB_CODE, 298 ARM_MAP_ROMLIB_DATA, 299 #endif 300 #if USE_COHERENT_MEM 301 ARM_MAP_BL_COHERENT_RAM, 302 #endif 303 {0} 304 }; 305 306 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 307 308 enable_mmu_el3(0); 309 310 arm_setup_romlib(); 311 } 312 313 void bl31_plat_arch_setup(void) 314 { 315 arm_bl31_plat_arch_setup(); 316 } 317