1 /*
2 * Copyright (c) 2017-2024, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <drivers/generic_delay_timer.h>
10 #include <drivers/partition/partition.h>
11 #include <lib/fconf/fconf.h>
12 #include <lib/fconf/fconf_dyn_cfg_getter.h>
13 #include <plat/arm/common/plat_arm.h>
14 #include <plat/common/platform.h>
15 #include <platform_def.h>
16
17 #pragma weak bl2_el3_early_platform_setup
18 #pragma weak bl2_el3_plat_arch_setup
19 #pragma weak bl2_el3_plat_prepare_exit
20
21 #define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \
22 bl2_el3_tzram_layout.total_base, \
23 bl2_el3_tzram_layout.total_size, \
24 MT_MEMORY | MT_RW | MT_SECURE)
25
26 static meminfo_t bl2_el3_tzram_layout;
27
28 /*
29 * Perform arm specific early platform setup. At this moment we only initialize
30 * the console and the memory layout.
31 */
arm_bl2_el3_early_platform_setup(void)32 void arm_bl2_el3_early_platform_setup(void)
33 {
34 /* Initialize the console to provide early debug support */
35 arm_console_boot_init();
36
37 /*
38 * Allow BL2 to see the whole Trusted RAM. This is determined
39 * statically since we cannot rely on BL1 passing this information
40 * in the RESET_TO_BL2 case.
41 */
42 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE;
43 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE;
44
45 /* Initialise the IO layer and register platform IO devices */
46 plat_arm_io_setup();
47 }
48
bl2_el3_early_platform_setup(u_register_t arg0 __unused,u_register_t arg1 __unused,u_register_t arg2 __unused,u_register_t arg3 __unused)49 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
50 u_register_t arg1 __unused,
51 u_register_t arg2 __unused,
52 u_register_t arg3 __unused)
53 {
54 arm_bl2_el3_early_platform_setup();
55 #if !HW_ASSISTED_COHERENCY
56 /*
57 * Initialize Interconnect for this cluster during cold boot.
58 * No need for locks as no other CPU is active.
59 */
60 plat_arm_interconnect_init();
61 /*
62 * Enable Interconnect coherency for the primary CPU's cluster.
63 */
64 plat_arm_interconnect_enter_coherency();
65 #endif
66 generic_delay_timer_init();
67 }
68
69 #if ARM_FW_CONFIG_LOAD_ENABLE
70 /*************************************************************************************
71 * FW CONFIG load function for BL2 when RESET_TO_BL2=1 && ARM_FW_CONFIG_LOAD_ENABLE=1
72 *************************************************************************************/
arm_bl2_el3_plat_config_load(void)73 void arm_bl2_el3_plat_config_load(void)
74 {
75 int ret;
76 const struct dyn_cfg_dtb_info_t *fw_config_info;
77
78 /* Set global DTB info for fixed fw_config information */
79 set_config_info(PLAT_FW_CONFIG_BASE, ~0UL, PLAT_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
80
81 /* Fill the device tree information struct with the info from the config dtb */
82 ret = fconf_load_config(FW_CONFIG_ID);
83 if (ret < 0) {
84 ERROR("Loading of FW_CONFIG failed %d\n", ret);
85 plat_error_handler(ret);
86 }
87
88 /*
89 * FW_CONFIG loaded successfully. Check the FW_CONFIG device tree parsing
90 * is successful.
91 */
92 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
93 if (fw_config_info == NULL) {
94 ret = -1;
95 ERROR("Invalid FW_CONFIG address\n");
96 plat_error_handler(ret);
97 }
98 ret = fconf_populate_dtb_registry(fw_config_info->config_addr);
99 if (ret < 0) {
100 ERROR("Parsing of FW_CONFIG failed %d\n", ret);
101 plat_error_handler(ret);
102 }
103 }
104 #endif /* ARM_FW_CONFIG_LOAD_ENABLE */
105
106 /*******************************************************************************
107 * Perform the very early platform specific architectural setup here. At the
108 * moment this is only initializes the mmu in a quick and dirty way.
109 ******************************************************************************/
arm_bl2_el3_plat_arch_setup(void)110 void arm_bl2_el3_plat_arch_setup(void)
111 {
112
113 #if USE_COHERENT_MEM
114 /* Ensure ARM platforms dont use coherent memory
115 * in RESET_TO_BL2
116 */
117 assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U);
118 #endif
119
120 const mmap_region_t bl_regions[] = {
121 MAP_BL2_EL3_TOTAL,
122 ARM_MAP_BL_RO,
123 {0}
124 };
125
126 setup_page_tables(bl_regions, plat_arm_get_mmap());
127
128 #ifdef __aarch64__
129 enable_mmu_el3(0);
130 #else
131 enable_mmu_svc_mon(0);
132 #endif
133 }
134
bl2_el3_plat_arch_setup(void)135 void bl2_el3_plat_arch_setup(void)
136 {
137 int __maybe_unused ret;
138 arm_bl2_el3_plat_arch_setup();
139 #if ARM_GPT_SUPPORT
140 ret = gpt_partition_init();
141 if (ret != 0) {
142 ERROR("GPT partition initialisation failed!\n");
143 panic();
144 }
145 #endif /* ARM_GPT_SUPPORT */
146 }
147
bl2_el3_plat_prepare_exit(void)148 void bl2_el3_plat_prepare_exit(void)
149 {
150 }
151