1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <generic_delay_timer.h> 7 #include <plat_arm.h> 8 #include <platform.h> 9 10 #pragma weak bl2_el3_early_platform_setup 11 #pragma weak bl2_el3_plat_arch_setup 12 #pragma weak bl2_el3_plat_prepare_exit 13 14 static meminfo_t bl2_el3_tzram_layout; 15 16 /* 17 * Perform arm specific early platform setup. At this moment we only initialize 18 * the console and the memory layout. 19 */ 20 void arm_bl2_el3_early_platform_setup(void) 21 { 22 /* Initialize the console to provide early debug support */ 23 arm_console_boot_init(); 24 25 /* 26 * Allow BL2 to see the whole Trusted RAM. This is determined 27 * statically since we cannot rely on BL1 passing this information 28 * in the BL2_AT_EL3 case. 29 */ 30 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE; 31 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE; 32 33 /* Initialise the IO layer and register platform IO devices */ 34 plat_arm_io_setup(); 35 } 36 37 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 38 u_register_t arg1 __unused, 39 u_register_t arg2 __unused, 40 u_register_t arg3 __unused) 41 { 42 arm_bl2_el3_early_platform_setup(); 43 44 /* 45 * Initialize Interconnect for this cluster during cold boot. 46 * No need for locks as no other CPU is active. 47 */ 48 plat_arm_interconnect_init(); 49 /* 50 * Enable Interconnect coherency for the primary CPU's cluster. 51 */ 52 plat_arm_interconnect_enter_coherency(); 53 54 generic_delay_timer_init(); 55 } 56 57 /******************************************************************************* 58 * Perform the very early platform specific architectural setup here. At the 59 * moment this is only initializes the mmu in a quick and dirty way. 60 ******************************************************************************/ 61 void arm_bl2_el3_plat_arch_setup(void) 62 { 63 arm_setup_page_tables(bl2_el3_tzram_layout.total_base, 64 bl2_el3_tzram_layout.total_size, 65 BL_CODE_BASE, 66 BL_CODE_END, 67 BL_RO_DATA_BASE, 68 BL_RO_DATA_END 69 #if USE_COHERENT_MEM 70 , BL_COHERENT_RAM_BASE, 71 BL_COHERENT_RAM_END 72 #endif 73 ); 74 75 #ifdef AARCH32 76 enable_mmu_secure(0); 77 #else 78 enable_mmu_el3(0); 79 #endif 80 } 81 82 void bl2_el3_plat_arch_setup(void) 83 { 84 arm_bl2_el3_plat_arch_setup(); 85 } 86 87 void bl2_el3_plat_prepare_exit(void) 88 { 89 } 90