1 /*
2 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <plat/common/platform.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <drivers/arm/ccn.h>
15 #include <drivers/arm/css/sds.h>
16 #include <lib/utils_def.h>
17 #include <plat/arm/common/plat_arm.h>
18 #include <plat/common/platform.h>
19 #include <drivers/arm/sbsa.h>
20
21 #if SPM_MM
22 #include <services/spm_mm_partition.h>
23 #endif
24
25 /*
26 * Table of regions for different BL stages to map using the MMU.
27 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
28 * arm_configure_mmu_elx() will give the available subset of that.
29 */
30 #if IMAGE_BL1
31 const mmap_region_t plat_arm_mmap[] = {
32 ARM_MAP_SHARED_RAM,
33 TC_MAP_NS_DRAM1,
34 TC_FLASH0_RO,
35 TC_MAP_DEVICE,
36 #if TRANSFER_LIST
37 TC_MAP_EL3_FW_HANDOFF,
38 #endif
39 {0}
40 };
41 #endif
42 #if IMAGE_BL2
43 const mmap_region_t plat_arm_mmap[] = {
44 ARM_MAP_SHARED_RAM,
45 TC_FLASH0_RO,
46 ARM_V2M_MAP_MEM_PROTECT,
47 TC_MAP_DEVICE,
48 TC_MAP_NS_DRAM1,
49 #if defined(SPD_spmd)
50 TC_MAP_TZC_DRAM1,
51 #endif
52 #if ARM_BL31_IN_DRAM
53 ARM_MAP_BL31_SEC_DRAM,
54 #endif
55 #if SPM_MM
56 ARM_SP_IMAGE_MMAP,
57 #endif
58 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
59 ARM_MAP_BL1_RW,
60 #endif
61 #ifdef SPD_opteed
62 ARM_MAP_OPTEE_CORE_MEM,
63 ARM_OPTEE_PAGEABLE_LOAD_MEM,
64 #endif
65 #if TRANSFER_LIST
66 TC_MAP_EL3_FW_HANDOFF,
67 #endif
68 {0}
69 };
70 #endif
71 #if IMAGE_BL31
72 const mmap_region_t plat_arm_mmap[] = {
73 ARM_MAP_SHARED_RAM,
74 V2M_MAP_IOFPGA,
75 ARM_V2M_MAP_MEM_PROTECT,
76 TC_MAP_DEVICE,
77 PLAT_DTB_DRAM_NS,
78 #if SPM_MM
79 ARM_SPM_BUF_EL3_MMAP,
80 #endif
81 #if TRANSFER_LIST
82 TC_MAP_FW_NS_HANDOFF,
83 TC_MAP_EL3_FW_HANDOFF,
84 #endif
85 {0}
86 };
87
88 #if SPM_MM && defined(IMAGE_BL31)
89 const mmap_region_t plat_arm_secure_partition_mmap[] = {
90 PLAT_ARM_SECURE_MAP_DEVICE,
91 ARM_SP_IMAGE_MMAP,
92 ARM_SP_IMAGE_NS_BUF_MMAP,
93 ARM_SP_CPER_BUF_MMAP,
94 ARM_SP_IMAGE_RW_MMAP,
95 ARM_SPM_BUF_EL0_MMAP,
96 {0}
97 };
98 #endif /* SPM_MM && defined(IMAGE_BL31) */
99 #endif
100
101 ARM_CASSERT_MMAP
102
103 #if SPM_MM && defined(IMAGE_BL31)
104 /*
105 * Boot information passed to a secure partition during initialisation. Linear
106 * indices in MP information will be filled at runtime.
107 */
108 static spm_mm_mp_info_t sp_mp_info[] = {
109 [0] = {0x81000000, 0},
110 [1] = {0x81000100, 0},
111 [2] = {0x81000200, 0},
112 [3] = {0x81000300, 0},
113 [4] = {0x81010000, 0},
114 [5] = {0x81010100, 0},
115 [6] = {0x81010200, 0},
116 [7] = {0x81010300, 0},
117 };
118
119 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
120 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
121 .h.version = VERSION_1,
122 .h.size = sizeof(spm_mm_boot_info_t),
123 .h.attr = 0,
124 .sp_mem_base = ARM_SP_IMAGE_BASE,
125 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
126 .sp_image_base = ARM_SP_IMAGE_BASE,
127 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
128 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
129 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
130 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
131 .sp_image_size = ARM_SP_IMAGE_SIZE,
132 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
133 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
134 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
135 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
136 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
137 .num_cpus = PLATFORM_CORE_COUNT,
138 .mp_info = &sp_mp_info[0],
139 };
140
plat_get_secure_partition_mmap(void * cookie)141 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
142 {
143 return plat_arm_secure_partition_mmap;
144 }
145
plat_get_secure_partition_boot_info(void * cookie)146 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
147 void *cookie)
148 {
149 return &plat_arm_secure_partition_boot_info;
150 }
151 #endif /* SPM_MM && defined(IMAGE_BL31) */
152
153 #if TRUSTED_BOARD_BOOT || MEASURED_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)154 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
155 {
156 assert(heap_addr != NULL);
157 assert(heap_size != NULL);
158
159 return arm_get_mbedtls_heap(heap_addr, heap_size);
160 }
161 #endif
162
plat_arm_secure_wdt_start(void)163 void plat_arm_secure_wdt_start(void)
164 {
165 sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT);
166 }
167
plat_arm_secure_wdt_stop(void)168 void plat_arm_secure_wdt_stop(void)
169 {
170 sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE);
171 }
172
plat_arm_secure_wdt_refresh(void)173 void plat_arm_secure_wdt_refresh(void)
174 {
175 sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE);
176 }
177
178 static sds_region_desc_t tc_sds_regions[] = {
179 { .base = PLAT_ARM_SDS_MEM_BASE },
180 { .base = PLAT_ARM_RSE_AP_SDS_MEM_BASE },
181 };
182
plat_sds_get_regions(unsigned int * region_count)183 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
184 {
185 *region_count = ARRAY_SIZE(tc_sds_regions);
186
187 return tc_sds_regions;
188 }
189