1 /* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <cortex_a520.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/board_css_def.h> 14 #include <plat/arm/board/common/v2m_def.h> 15 16 /* 17 * arm_def.h depends on the platform system counter macros, so must define the 18 * platform macros before including arm_def.h. 19 */ 20 #if TARGET_PLATFORM == 4 21 #ifdef ARM_SYS_CNTCTL_BASE 22 #error "error: ARM_SYS_CNTCTL_BASE is defined prior to the PLAT_ARM_SYS_CNTCTL_BASE definition" 23 #endif 24 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0x47000000) 25 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0x47010000) 26 #endif 27 28 #include <plat/arm/common/arm_def.h> 29 30 #include <plat/arm/common/arm_spm_def.h> 31 #include <plat/arm/css/common/css_def.h> 32 #include <plat/arm/soc/common/soc_css_def.h> 33 #include <plat/common/common_def.h> 34 35 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 36 37 /* 38 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 39 * its base is ARM_AP_TZC_DRAM1_BASE. 40 * 41 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 42 * - BL32_BASE when SPD_spmd is enabled 43 * - Region to load secure partitions 44 * 45 * 46 * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE 47 * | DTB | 48 * | (32K) | 49 * 0x8000_8000 ------------------ 50 * | NT_FW_CONFIG | 51 * | (4KB) | 52 * 0x8000_9000 ------------------ 53 * | ... | 54 * 0xf8a0_0000 ------------------ TC_NS_FWU_BASE 55 * | FWU shmem | 56 * | (4MB) | 57 * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE 58 * | OP-TEE shmem | 59 * | (2MB) | 60 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 61 * | | 62 * | SPMC | 63 * | SP | 64 * | (96MB) | 65 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 66 * | AP | 67 * | EL3 Monitor | 68 * | SCP | 69 * | (16MB) | 70 * 0xFFFF_FFFF ------------------ 71 * 72 * 73 */ 74 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 75 TC_TZC_DRAM1_SIZE) 76 #define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */ 77 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 78 TC_TZC_DRAM1_SIZE - 1) 79 80 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 81 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 82 ARM_TZC_DRAM1_SIZE - \ 83 TC_TZC_DRAM1_SIZE) 84 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1) 85 86 #define TC_NS_OPTEE_SIZE (2 * SZ_1M) 87 #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) 88 #define TC_NS_FWU_SIZE (4 * SZ_1M) 89 #define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE) 90 91 /* 92 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 93 */ 94 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 95 TC_NS_DRAM1_BASE, \ 96 TC_NS_DRAM1_SIZE, \ 97 MT_MEMORY | MT_RW | MT_NS) 98 99 100 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 101 TC_TZC_DRAM1_BASE, \ 102 TC_TZC_DRAM1_SIZE, \ 103 MT_MEMORY | MT_RW | MT_SECURE) 104 105 #define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE 106 #define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000) 107 108 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 109 PLAT_HW_CONFIG_DTB_BASE, \ 110 PLAT_ARM_HW_CONFIG_SIZE, \ 111 MT_MEMORY | MT_RO | MT_NS) 112 /* 113 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 114 * max size of BL32 image. 115 */ 116 #if defined(SPD_spmd) 117 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 118 119 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 120 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 121 #endif 122 123 /* 124 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 125 * plat_arm_mmap array defined for each BL stage. 126 */ 127 #if defined(IMAGE_BL31) 128 # if SPM_MM 129 # define PLAT_ARM_MMAP_ENTRIES 9 130 # define MAX_XLAT_TABLES 7 131 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 132 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 133 # else 134 # define PLAT_ARM_MMAP_ENTRIES 8 135 # define MAX_XLAT_TABLES 8 136 # endif 137 #elif defined(IMAGE_BL32) 138 # define PLAT_ARM_MMAP_ENTRIES 8 139 # define MAX_XLAT_TABLES 5 140 #elif !USE_ROMLIB 141 # define PLAT_ARM_MMAP_ENTRIES 11 142 # define MAX_XLAT_TABLES 7 143 #else 144 # define PLAT_ARM_MMAP_ENTRIES 12 145 # define MAX_XLAT_TABLES 6 146 #endif 147 148 /* 149 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 150 * plus a little space for growth. 151 */ 152 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 153 154 /* 155 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 156 */ 157 158 #if USE_ROMLIB 159 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 160 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 161 #else 162 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 163 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 164 #endif 165 166 /* 167 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 168 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 169 * and MEASURED_BOOT is enabled. 170 */ 171 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 172 173 174 /* 175 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 176 * calculated using the current BL31 PROGBITS debug size plus the sizes of 177 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 178 * MEASURED_BOOT is enabled. 179 */ 180 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 181 182 /* 183 * Size of cacheable stacks 184 */ 185 #if defined(IMAGE_BL1) 186 # define PLATFORM_STACK_SIZE 0x1000 187 #elif defined(IMAGE_BL2) 188 # define PLATFORM_STACK_SIZE 0x1000 189 #elif defined(IMAGE_BL2U) 190 # define PLATFORM_STACK_SIZE 0x400 191 #elif defined(IMAGE_BL31) 192 # if SPM_MM 193 # define PLATFORM_STACK_SIZE 0x500 194 # else 195 # define PLATFORM_STACK_SIZE 0xa00 196 # endif 197 #elif defined(IMAGE_BL32) 198 # define PLATFORM_STACK_SIZE 0x440 199 #endif 200 201 /* 202 * In the current implementation the RoT Service request that requires the 203 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 204 * maximum required buffer size is calculated based on the platform-specific 205 * needs of this request. 206 */ 207 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500 208 209 #define TC_DEVICE_BASE 0x21000000 210 #define TC_DEVICE_SIZE 0x5f000000 211 212 #if defined(TARGET_FLAVOUR_FPGA) 213 #undef V2M_FLASH0_BASE 214 #undef V2M_FLASH0_SIZE 215 #define V2M_FLASH0_BASE UL(0x0C000000) 216 #define V2M_FLASH0_SIZE UL(0x02000000) 217 #endif 218 219 // TC_MAP_DEVICE covers different peripherals 220 // available to the platform 221 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 222 TC_DEVICE_BASE, \ 223 TC_DEVICE_SIZE, \ 224 MT_DEVICE | MT_RW | MT_SECURE) 225 226 227 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 228 V2M_FLASH0_SIZE, \ 229 MT_DEVICE | MT_RO | MT_SECURE) 230 231 #define PLAT_ARM_NSTIMER_FRAME_ID 0 232 233 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 234 235 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 236 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 237 238 #define PLAT_ARM_NSRAM_BASE 0x06000000 239 #if TARGET_FLAVOUR_FVP 240 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 241 #else /* TARGET_FLAVOUR_FPGA */ 242 #define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */ 243 #endif /* TARGET_FLAVOUR_FPGA */ 244 245 #if TARGET_PLATFORM <= 2 246 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 247 #elif TARGET_PLATFORM >= 3 248 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 249 #endif /* TARGET_PLATFORM >= 3 */ 250 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 251 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 252 253 #define TC_NS_MTE_SIZE (256 * SZ_1M) 254 /* the SCP puts the carveout at the end of DRAM2 */ 255 #define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE) 256 257 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 258 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 259 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 260 GIC_HIGHEST_SEC_PRIORITY, grp, \ 261 GIC_INTR_CFG_LEVEL) 262 263 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 264 PLAT_SP_IMAGE_NS_BUF_SIZE) 265 266 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 267 268 /******************************************************************************* 269 * Memprotect definitions 270 ******************************************************************************/ 271 /* PSCI memory protect definitions: 272 * This variable is stored in a non-secure flash because some ARM reference 273 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 274 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 275 */ 276 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 277 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 278 279 /* Secure Watchdog Constants */ 280 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 281 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 282 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 283 #define SBSA_SECURE_WDOG_INTID 86 284 285 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 286 287 /* Index of SDS region used in the communication with SCP */ 288 #define SDS_SCP_AP_REGION_ID U(0) 289 /* Index of SDS region used in the communication with RSE */ 290 #define SDS_RSE_AP_REGION_ID U(1) 291 /* 292 * Memory region for RSE's shared data storage (SDS) 293 * It is placed right after the SCMI payload area. 294 */ 295 #define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 296 CSS_SCMI_PAYLOAD_SIZE_MAX) 297 298 #define PLAT_ARM_CLUSTER_COUNT U(1) 299 #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 300 #define PLAT_MAX_CPUS_PER_CLUSTER U(14) 301 #else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 302 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 303 #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 304 #define PLAT_MAX_PE_PER_CPU U(1) 305 306 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 307 308 /* Message Handling Unit (MHU) base addresses */ 309 #if TARGET_PLATFORM <= 2 310 #define PLAT_CSS_MHU_BASE UL(0x45400000) 311 #elif TARGET_PLATFORM >= 3 312 #define PLAT_CSS_MHU_BASE UL(0x46000000) 313 #endif /* TARGET_PLATFORM >= 3 */ 314 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 315 316 /* AP<->RSS MHUs */ 317 #if TARGET_PLATFORM <= 2 318 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000) 319 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000) 320 #elif TARGET_PLATFORM == 3 321 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 322 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000) 323 #elif TARGET_PLATFORM == 4 324 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 325 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49010000) 326 #endif 327 328 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 329 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 330 331 /* 332 * Physical and virtual address space limits for MMU in AARCH64 333 */ 334 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 335 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 336 337 /* GIC related constants */ 338 #define PLAT_ARM_GICD_BASE UL(0x30000000) 339 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 340 #define PLAT_ARM_GICR_BASE UL(0x30080000) 341 342 /* 343 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 344 * SCP_BL2 size plus a little space for growth. 345 */ 346 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 347 348 /* 349 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 350 * SCP_BL2U size plus a little space for growth. 351 */ 352 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 353 354 #if TARGET_PLATFORM <= 2 355 /* TZC Related Constants */ 356 #define PLAT_ARM_TZC_BASE UL(0x25000000) 357 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 358 359 #define TZC400_OFFSET UL(0x1000000) 360 #define TZC400_COUNT 4 361 362 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 363 (n * TZC400_OFFSET)) 364 365 #define TZC_NSAID_DEFAULT U(0) 366 367 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 368 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 369 370 /* 371 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 372 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 373 * secure. The second and third regions gives non secure access to rest of DRAM. 374 */ 375 #define TC_TZC_REGIONS_DEF \ 376 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 377 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 378 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 379 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 380 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 381 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 382 #endif 383 384 /* virtual address used by dynamic mem_protect for chunk_base */ 385 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 386 387 #if ARM_GPT_SUPPORT 388 /* 389 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 390 * Offset of the FIP in the GPT image. BL1 component uses this option 391 * as it does not load the partition table to get the FIP base 392 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 393 * (i.e. after reserved sectors 0-47). 394 * Offset = 48 * 512 = 0x6000 395 */ 396 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 397 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 398 #endif /* ARM_GPT_SUPPORT */ 399 400 /* UART related constants */ 401 402 #define TC_UART0 0x2a400000 403 #define TC_UART1 0x2a410000 404 405 /* 406 * TODO: if any more undefs are needed, it's better to consider dropping the 407 * board_css_def.h include above 408 */ 409 #undef PLAT_ARM_BOOT_UART_BASE 410 #undef PLAT_ARM_RUN_UART_BASE 411 412 #undef PLAT_ARM_CRASH_UART_BASE 413 #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ 414 #undef PLAT_ARM_RUN_UART_CLK_IN_HZ 415 416 #if TARGET_FLAVOUR_FVP 417 #define PLAT_ARM_BOOT_UART_BASE TC_UART1 418 #define TC_UARTCLK 7372800 419 #else /* TARGET_FLAVOUR_FPGA */ 420 #define PLAT_ARM_BOOT_UART_BASE TC_UART0 421 #if TARGET_PLATFORM <= 2 422 #define TC_UARTCLK 5000000 423 #elif TARGET_PLATFORM >= 3 424 #define TC_UARTCLK 3750000 425 #endif /* TARGET_PLATFORM >= 3 */ 426 #undef ARM_CONSOLE_BAUDRATE 427 #define ARM_CONSOLE_BAUDRATE 38400 428 #endif /* TARGET_FLAVOUR_FPGA */ 429 430 #define PLAT_ARM_RUN_UART_BASE TC_UART0 431 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 432 433 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK 434 #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK 435 436 #if TARGET_PLATFORM == 3 437 #define NCI_BASE_ADDR UL(0x4F000000) 438 #ifdef TARGET_FLAVOUR_FPGA 439 #define MCN_ADDRESS_SPACE_SIZE 0x00120000 440 #else 441 #define MCN_ADDRESS_SPACE_SIZE 0x00130000 442 #endif /* TARGET_FLAVOUR_FPGA */ 443 #define MCN_OFFSET_IN_NCI 0x00C90000 444 #define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI) 445 #define MCN_PMU_OFFSET 0x000C4000 446 #define MCN_MICROARCH_OFFSET 0x000E4000 447 #define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET) 448 #define MCN_SCR_OFFSET 0x4 449 #define MCN_SCR_PMU_BIT 10 450 #define MCN_INSTANCES 4 451 #define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \ 452 (n * MCN_ADDRESS_SPACE_SIZE) + \ 453 MCN_PMU_OFFSET) 454 #define MCN_MPAM_NS_OFFSET 0x000D0000 455 #define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET) 456 #define MCN_MPAM_S_OFFSET 0x000D4000 457 #define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET) 458 #define MPAM_SLCCFG_CTL_OFFSET 0x00003018 459 #define SLC_RDALLOCMODE_SHIFT 8 460 #define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT) 461 #define SLC_WRALLOCMODE_SHIFT 12 462 #define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT) 463 464 #define SLC_DONT_ALLOC 0 465 #define SLC_ALWAYS_ALLOC 1 466 #define SLC_ALLOC_BUS_SIGNAL_ATTR 2 467 468 #define MCN_CONFIG_OFFSET 0x204 469 #define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET) 470 #define MCN_CONFIG_SLC_PRESENT_BIT 3 471 472 /* 473 * TC3 CPUs have the same definitions for: 474 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1 475 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT 476 * Define the common macros for easier using. 477 */ 478 #define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1 479 #define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT 480 #endif /* TARGET_PLATFORM == 3 */ 481 482 #define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12) 483 484 #endif /* PLATFORM_DEF_H */ 485