1 /* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/board/common/board_css_def.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/css/common/css_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 #include <plat/common/common_def.h> 19 20 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 21 22 /* 23 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 24 * its base is ARM_AP_TZC_DRAM1_BASE. 25 * 26 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 27 * - BL32_BASE when SPD_spmd is enabled 28 * - Region to load secure partitions 29 * 30 * 31 * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE 32 * | DTB | 33 * | (32K) | 34 * 0x8000_8000 ------------------ 35 * | ... | 36 * 0xf8a0_0000 ------------------ TC_NS_FWU_BASE 37 * | FWU shmem | 38 * | (4MB) | 39 * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE 40 * | OP-TEE shmem | 41 * | (2MB) | 42 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 43 * | | 44 * | SPMC | 45 * | SP | 46 * | (96MB) | 47 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 48 * | AP | 49 * | EL3 Monitor | 50 * | SCP | 51 * | (16MB) | 52 * 0xFFFF_FFFF ------------------ 53 * 54 * 55 */ 56 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 57 TC_TZC_DRAM1_SIZE) 58 #define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */ 59 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 60 TC_TZC_DRAM1_SIZE - 1) 61 62 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 63 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 64 ARM_TZC_DRAM1_SIZE - \ 65 TC_TZC_DRAM1_SIZE) 66 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1) 67 68 #define TC_NS_OPTEE_SIZE (2 * SZ_1M) 69 #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) 70 #define TC_NS_FWU_SIZE (4 * SZ_1M) 71 #define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE) 72 73 /* 74 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 75 */ 76 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 77 TC_NS_DRAM1_BASE, \ 78 TC_NS_DRAM1_SIZE, \ 79 MT_MEMORY | MT_RW | MT_NS) 80 81 82 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 83 TC_TZC_DRAM1_BASE, \ 84 TC_TZC_DRAM1_SIZE, \ 85 MT_MEMORY | MT_RW | MT_SECURE) 86 87 #define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE 88 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 89 90 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 91 PLAT_HW_CONFIG_DTB_BASE, \ 92 PLAT_HW_CONFIG_DTB_SIZE, \ 93 MT_MEMORY | MT_RO | MT_NS) 94 /* 95 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 96 * max size of BL32 image. 97 */ 98 #if defined(SPD_spmd) 99 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 100 101 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 102 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 103 #endif 104 105 /* 106 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 107 * plat_arm_mmap array defined for each BL stage. 108 */ 109 #if defined(IMAGE_BL31) 110 # if SPM_MM 111 # define PLAT_ARM_MMAP_ENTRIES 9 112 # define MAX_XLAT_TABLES 7 113 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 114 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 115 # else 116 # define PLAT_ARM_MMAP_ENTRIES 8 117 # define MAX_XLAT_TABLES 8 118 # endif 119 #elif defined(IMAGE_BL32) 120 # define PLAT_ARM_MMAP_ENTRIES 8 121 # define MAX_XLAT_TABLES 5 122 #elif !USE_ROMLIB 123 # define PLAT_ARM_MMAP_ENTRIES 11 124 # define MAX_XLAT_TABLES 7 125 #else 126 # define PLAT_ARM_MMAP_ENTRIES 12 127 # define MAX_XLAT_TABLES 6 128 #endif 129 130 /* 131 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 132 * plus a little space for growth. 133 */ 134 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 135 136 /* 137 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 138 */ 139 140 #if USE_ROMLIB 141 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 142 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 143 #else 144 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 145 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 146 #endif 147 148 /* 149 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 150 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 151 * and MEASURED_BOOT is enabled. 152 */ 153 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 154 155 156 /* 157 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 158 * calculated using the current BL31 PROGBITS debug size plus the sizes of 159 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 160 * MEASURED_BOOT is enabled. 161 */ 162 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 163 164 /* 165 * Size of cacheable stacks 166 */ 167 #if defined(IMAGE_BL1) 168 # if TRUSTED_BOARD_BOOT 169 # define PLATFORM_STACK_SIZE 0x1000 170 # else 171 # define PLATFORM_STACK_SIZE 0x440 172 # endif 173 #elif defined(IMAGE_BL2) 174 # if TRUSTED_BOARD_BOOT 175 # define PLATFORM_STACK_SIZE 0x1000 176 # else 177 # define PLATFORM_STACK_SIZE 0x400 178 # endif 179 #elif defined(IMAGE_BL2U) 180 # define PLATFORM_STACK_SIZE 0x400 181 #elif defined(IMAGE_BL31) 182 # if SPM_MM 183 # define PLATFORM_STACK_SIZE 0x500 184 # else 185 # define PLATFORM_STACK_SIZE 0xa00 186 # endif 187 #elif defined(IMAGE_BL32) 188 # define PLATFORM_STACK_SIZE 0x440 189 #endif 190 191 /* 192 * In the current implementation the RoT Service request that requires the 193 * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 194 * maximum required buffer size is calculated based on the platform-specific 195 * needs of this request. 196 */ 197 #define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500 198 199 #define TC_DEVICE_BASE 0x21000000 200 #define TC_DEVICE_SIZE 0x5f000000 201 202 #if defined(TARGET_FLAVOUR_FPGA) 203 #undef V2M_FLASH0_BASE 204 #undef V2M_FLASH0_SIZE 205 #define V2M_FLASH0_BASE UL(0x0C000000) 206 #define V2M_FLASH0_SIZE UL(0x02000000) 207 #endif 208 209 // TC_MAP_DEVICE covers different peripherals 210 // available to the platform 211 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 212 TC_DEVICE_BASE, \ 213 TC_DEVICE_SIZE, \ 214 MT_DEVICE | MT_RW | MT_SECURE) 215 216 217 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 218 V2M_FLASH0_SIZE, \ 219 MT_DEVICE | MT_RO | MT_SECURE) 220 221 #define PLAT_ARM_NSTIMER_FRAME_ID 0 222 223 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 224 225 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 226 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 227 228 #define PLAT_ARM_NSRAM_BASE 0x06000000 229 #if TARGET_FLAVOUR_FVP 230 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 231 #else /* TARGET_FLAVOUR_FPGA */ 232 #define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */ 233 #endif /* TARGET_FLAVOUR_FPGA */ 234 235 #if TARGET_PLATFORM <= 2 236 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 237 #elif TARGET_PLATFORM == 3 238 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 239 #endif /* TARGET_PLATFORM == 3 */ 240 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 241 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 242 243 #define TC_NS_MTE_SIZE (256 * SZ_1M) 244 /* the SCP puts the carveout at the end of DRAM2 */ 245 #define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE) 246 247 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 248 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 249 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 250 GIC_HIGHEST_SEC_PRIORITY, grp, \ 251 GIC_INTR_CFG_LEVEL) 252 253 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 254 PLAT_SP_IMAGE_NS_BUF_SIZE) 255 256 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 257 258 /******************************************************************************* 259 * Memprotect definitions 260 ******************************************************************************/ 261 /* PSCI memory protect definitions: 262 * This variable is stored in a non-secure flash because some ARM reference 263 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 264 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 265 */ 266 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 267 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 268 269 /* Secure Watchdog Constants */ 270 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 271 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 272 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 273 #define SBSA_SECURE_WDOG_INTID 86 274 275 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 276 277 /* Index of SDS region used in the communication with SCP */ 278 #define SDS_SCP_AP_REGION_ID U(0) 279 /* Index of SDS region used in the communication with RSS */ 280 #define SDS_RSS_AP_REGION_ID U(1) 281 /* 282 * Memory region for RSS's shared data storage (SDS) 283 * It is placed right after the SCMI payload area. 284 */ 285 #define PLAT_ARM_RSS_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 286 CSS_SCMI_PAYLOAD_SIZE_MAX) 287 288 #define PLAT_ARM_CLUSTER_COUNT U(1) 289 #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 290 #define PLAT_MAX_CPUS_PER_CLUSTER U(14) 291 #else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 292 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 293 #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 294 #define PLAT_MAX_PE_PER_CPU U(1) 295 296 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 297 298 /* Message Handling Unit (MHU) base addresses */ 299 #if TARGET_PLATFORM <= 2 300 #define PLAT_CSS_MHU_BASE UL(0x45400000) 301 #elif TARGET_PLATFORM == 3 302 #define PLAT_CSS_MHU_BASE UL(0x46000000) 303 #endif /* TARGET_PLATFORM == 3 */ 304 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 305 306 /* TC2: AP<->RSS MHUs */ 307 #define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000) 308 #define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000) 309 310 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 311 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 312 313 /* 314 * Physical and virtual address space limits for MMU in AARCH64 315 */ 316 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 317 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 318 319 /* GIC related constants */ 320 #define PLAT_ARM_GICD_BASE UL(0x30000000) 321 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 322 #define PLAT_ARM_GICR_BASE UL(0x30080000) 323 324 /* 325 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 326 * SCP_BL2 size plus a little space for growth. 327 */ 328 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 329 330 /* 331 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 332 * SCP_BL2U size plus a little space for growth. 333 */ 334 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 335 336 /* TZC Related Constants */ 337 #define PLAT_ARM_TZC_BASE UL(0x25000000) 338 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 339 340 #define TZC400_OFFSET UL(0x1000000) 341 #define TZC400_COUNT 4 342 343 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 344 (n * TZC400_OFFSET)) 345 346 #define TZC_NSAID_DEFAULT U(0) 347 348 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 349 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 350 351 /* 352 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 353 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 354 * secure. The second and third regions gives non secure access to rest of DRAM. 355 */ 356 #define TC_TZC_REGIONS_DEF \ 357 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 358 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 359 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 360 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 361 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 362 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 363 364 /* virtual address used by dynamic mem_protect for chunk_base */ 365 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 366 367 #if ARM_GPT_SUPPORT 368 /* 369 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 370 * Offset of the FIP in the GPT image. BL1 component uses this option 371 * as it does not load the partition table to get the FIP base 372 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 373 * (i.e. after reserved sectors 0-47). 374 * Offset = 48 * 512 = 0x6000 375 */ 376 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 377 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 378 #endif /* ARM_GPT_SUPPORT */ 379 380 /* UART related constants */ 381 382 #define TC_UART0 0x2a400000 383 #define TC_UART1 0x2a410000 384 385 /* 386 * TODO: if any more undefs are needed, it's better to consider dropping the 387 * board_css_def.h include above 388 */ 389 #undef PLAT_ARM_BOOT_UART_BASE 390 #undef PLAT_ARM_RUN_UART_BASE 391 #undef PLAT_ARM_SP_MIN_RUN_UART_BASE 392 #define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE 393 394 #undef PLAT_ARM_CRASH_UART_BASE 395 #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ 396 #undef PLAT_ARM_RUN_UART_CLK_IN_HZ 397 398 #if TARGET_FLAVOUR_FVP 399 #define PLAT_ARM_BOOT_UART_BASE TC_UART1 400 #define TC_UARTCLK 7372800 401 #else /* TARGET_FLAVOUR_FPGA */ 402 #define PLAT_ARM_BOOT_UART_BASE TC_UART0 403 #if TARGET_PLATFORM <= 2 404 #define TC_UARTCLK 5000000 405 #elif TARGET_PLATFORM >= 3 406 #define TC_UARTCLK 3750000 407 #endif /* TARGET_PLATFORM >= 3 */ 408 #undef ARM_CONSOLE_BAUDRATE 409 #define ARM_CONSOLE_BAUDRATE 38400 410 #endif /* TARGET_FLAVOUR_FPGA */ 411 412 #define PLAT_ARM_RUN_UART_BASE TC_UART0 413 #define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE 414 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 415 416 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK 417 #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK 418 419 #endif /* PLATFORM_DEF_H */ 420