1 /* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/board/common/board_css_def.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/css/common/css_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 #include <plat/common/common_def.h> 19 20 #define PLATFORM_CORE_COUNT 8 21 22 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 23 24 /* 25 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 26 * its base is ARM_AP_TZC_DRAM1_BASE. 27 * 28 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 29 * - BL32_BASE when SPD_spmd is enabled 30 * - Region to load secure partitions 31 * 32 * 33 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 34 * | | 35 * | SPMC | 36 * | SP | 37 * | (96MB) | 38 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 39 * | AP | 40 * | EL3 Monitor | 41 * | SCP | 42 * | (16MB) | 43 * 0xFFFF_FFFF ------------------ 44 * 45 * 46 */ 47 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 48 TC_TZC_DRAM1_SIZE) 49 #define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */ 50 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 51 TC_TZC_DRAM1_SIZE - 1) 52 53 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 54 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 55 ARM_TZC_DRAM1_SIZE - \ 56 TC_TZC_DRAM1_SIZE) 57 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \ 58 TC_NS_DRAM1_SIZE - 1) 59 60 /* 61 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 62 */ 63 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 64 TC_NS_DRAM1_BASE, \ 65 TC_NS_DRAM1_SIZE, \ 66 MT_MEMORY | MT_RW | MT_NS) 67 68 69 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 70 TC_TZC_DRAM1_BASE, \ 71 TC_TZC_DRAM1_SIZE, \ 72 MT_MEMORY | MT_RW | MT_SECURE) 73 74 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x83000000) 75 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 76 77 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 78 PLAT_HW_CONFIG_DTB_BASE, \ 79 PLAT_HW_CONFIG_DTB_SIZE, \ 80 MT_MEMORY | MT_RO | MT_NS) 81 /* 82 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 83 * max size of BL32 image. 84 */ 85 #if defined(SPD_spmd) 86 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 87 88 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 89 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 90 #endif 91 92 /* 93 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 94 * plat_arm_mmap array defined for each BL stage. 95 */ 96 #if defined(IMAGE_BL31) 97 # if SPM_MM 98 # define PLAT_ARM_MMAP_ENTRIES 9 99 # define MAX_XLAT_TABLES 7 100 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 101 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 102 # else 103 # define PLAT_ARM_MMAP_ENTRIES 8 104 # define MAX_XLAT_TABLES 8 105 # endif 106 #elif defined(IMAGE_BL32) 107 # define PLAT_ARM_MMAP_ENTRIES 8 108 # define MAX_XLAT_TABLES 5 109 #elif !USE_ROMLIB 110 # define PLAT_ARM_MMAP_ENTRIES 11 111 # define MAX_XLAT_TABLES 7 112 #else 113 # define PLAT_ARM_MMAP_ENTRIES 12 114 # define MAX_XLAT_TABLES 6 115 #endif 116 117 /* 118 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 119 * plus a little space for growth. 120 */ 121 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 122 123 /* 124 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 125 */ 126 127 #if USE_ROMLIB 128 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 129 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 130 #else 131 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 132 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 133 #endif 134 135 /* 136 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 137 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 138 * and MEASURED_BOOT is enabled. 139 */ 140 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 141 142 143 /* 144 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 145 * calculated using the current BL31 PROGBITS debug size plus the sizes of 146 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 147 * MEASURED_BOOT is enabled. 148 */ 149 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 150 151 /* 152 * Size of cacheable stacks 153 */ 154 #if defined(IMAGE_BL1) 155 # if TRUSTED_BOARD_BOOT 156 # define PLATFORM_STACK_SIZE 0x1000 157 # else 158 # define PLATFORM_STACK_SIZE 0x440 159 # endif 160 #elif defined(IMAGE_BL2) 161 # if TRUSTED_BOARD_BOOT 162 # define PLATFORM_STACK_SIZE 0x1000 163 # else 164 # define PLATFORM_STACK_SIZE 0x400 165 # endif 166 #elif defined(IMAGE_BL2U) 167 # define PLATFORM_STACK_SIZE 0x400 168 #elif defined(IMAGE_BL31) 169 # if SPM_MM 170 # define PLATFORM_STACK_SIZE 0x500 171 # else 172 # define PLATFORM_STACK_SIZE 0xa00 173 # endif 174 #elif defined(IMAGE_BL32) 175 # define PLATFORM_STACK_SIZE 0x440 176 #endif 177 178 /* 179 * In the current implementation the RoT Service request that requires the 180 * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 181 * maximum required buffer size is calculated based on the platform-specific 182 * needs of this request. 183 */ 184 #define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500 185 186 #define TC_DEVICE_BASE 0x21000000 187 #define TC_DEVICE_SIZE 0x5f000000 188 189 // TC_MAP_DEVICE covers different peripherals 190 // available to the platform 191 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 192 TC_DEVICE_BASE, \ 193 TC_DEVICE_SIZE, \ 194 MT_DEVICE | MT_RW | MT_SECURE) 195 196 197 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 198 V2M_FLASH0_SIZE, \ 199 MT_DEVICE | MT_RO | MT_SECURE) 200 201 #define PLAT_ARM_NSTIMER_FRAME_ID 0 202 203 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 204 205 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 206 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 207 208 #define PLAT_ARM_NSRAM_BASE 0x06000000 209 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 210 211 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 212 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 213 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 214 215 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 216 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 217 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 218 GIC_HIGHEST_SEC_PRIORITY, grp, \ 219 GIC_INTR_CFG_LEVEL) 220 221 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 222 PLAT_SP_IMAGE_NS_BUF_SIZE) 223 224 /******************************************************************************* 225 * Memprotect definitions 226 ******************************************************************************/ 227 /* PSCI memory protect definitions: 228 * This variable is stored in a non-secure flash because some ARM reference 229 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 230 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 231 */ 232 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 233 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 234 235 /* Secure Watchdog Constants */ 236 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 237 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 238 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 239 #define SBSA_SECURE_WDOG_INTID 86 240 241 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 242 243 /* Index of SDS region used in the communication with SCP */ 244 #define SDS_SCP_AP_REGION_ID U(0) 245 /* Index of SDS region used in the communication with RSS */ 246 #define SDS_RSS_AP_REGION_ID U(1) 247 /* 248 * Memory region for RSS's shared data storage (SDS) 249 * It is placed right after the SCMI payload area. 250 */ 251 #define PLAT_ARM_RSS_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 252 CSS_SCMI_PAYLOAD_SIZE_MAX) 253 254 #define PLAT_ARM_CLUSTER_COUNT U(1) 255 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 256 #define PLAT_MAX_PE_PER_CPU U(1) 257 258 /* Message Handling Unit (MHU) base addresses */ 259 #define PLAT_CSS_MHU_BASE UL(0x45400000) 260 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 261 262 /* TC2: AP<->RSS MHUs */ 263 #define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000) 264 #define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000) 265 266 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 267 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 268 269 /* 270 * Physical and virtual address space limits for MMU in AARCH64 271 */ 272 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 273 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 274 275 /* GIC related constants */ 276 #define PLAT_ARM_GICD_BASE UL(0x30000000) 277 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 278 #define PLAT_ARM_GICR_BASE UL(0x30080000) 279 280 /* 281 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 282 * SCP_BL2 size plus a little space for growth. 283 */ 284 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 285 286 /* 287 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 288 * SCP_BL2U size plus a little space for growth. 289 */ 290 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 291 292 /* TZC Related Constants */ 293 #define PLAT_ARM_TZC_BASE UL(0x25000000) 294 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 295 296 #define TZC400_OFFSET UL(0x1000000) 297 #define TZC400_COUNT 4 298 299 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 300 (n * TZC400_OFFSET)) 301 302 #define TZC_NSAID_DEFAULT U(0) 303 304 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 305 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 306 307 /* 308 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 309 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 310 * secure. The second and third regions gives non secure access to rest of DRAM. 311 */ 312 #define TC_TZC_REGIONS_DEF \ 313 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 314 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 315 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 316 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 317 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 318 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 319 320 /* virtual address used by dynamic mem_protect for chunk_base */ 321 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 322 323 #if ARM_GPT_SUPPORT 324 /* 325 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 326 * Offset of the FIP in the GPT image. BL1 component uses this option 327 * as it does not load the partition table to get the FIP base 328 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 329 * (i.e. after reserved sectors 0-47). 330 * Offset = 48 * 512 = 0x6000 331 */ 332 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 333 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 334 #endif /* ARM_GPT_SUPPORT */ 335 336 /* UART related constants */ 337 338 #undef PLAT_ARM_BOOT_UART_BASE 339 #define PLAT_ARM_BOOT_UART_BASE 0x2A410000 340 341 #undef PLAT_ARM_RUN_UART_BASE 342 #define PLAT_ARM_RUN_UART_BASE 0x2A400000 343 344 #undef PLAT_ARM_SP_MIN_RUN_UART_BASE 345 #define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE 346 347 #undef PLAT_ARM_CRASH_UART_BASE 348 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 349 350 #endif /* PLATFORM_DEF_H */ 351