1 /* 2 * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <nrd_ras.h> 10 #include <nrd_sdei.h> 11 12 struct nrd_ras_ev_map plat_ras_map[] = { 13 /* Non Secure base RAM ECC CE interrupt */ 14 {NRD_SDEI_DS_EVENT_0, NRD_CSS_NS_RAM_ECC_CE_INT, NRD_RAS_INTR_TYPE_SPI}, 15 16 /* Non Secure base RAM ECC UE interrupt */ 17 {NRD_SDEI_DS_EVENT_0, NRD_CSS_NS_RAM_ECC_UE_INT, NRD_RAS_INTR_TYPE_SPI}, 18 19 /* CPU 1-bit ECC CE error interrupt */ 20 {NRD_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, NRD_RAS_INTR_TYPE_PPI} 21 }; 22 23 /* RAS error record list definition, used by the common RAS framework. */ 24 struct err_record_info plat_err_records[] = { 25 /* Base element RAM Non-secure error record. */ 26 ERR_RECORD_MEMMAP_V1(NRD_CSS_NS_RAM_ERR_REC_BASE, 4, NULL, 27 &nrd_ras_sram_intr_handler, 0), 28 ERR_RECORD_SYSREG_V1(0, 1, NULL, &nrd_ras_cpu_intr_handler, 0), 29 }; 30 31 /* RAS error interrupt list definition, used by the common RAS framework. */ 32 struct ras_interrupt plat_ras_interrupts[] = { 33 { 34 .intr_number = PLAT_CORE_FAULT_IRQ, 35 .err_record = &plat_err_records[1], 36 }, { 37 .intr_number = NRD_CSS_NS_RAM_ECC_CE_INT, 38 .err_record = &plat_err_records[0], 39 }, { 40 .intr_number = NRD_CSS_NS_RAM_ECC_UE_INT, 41 .err_record = &plat_err_records[0], 42 }, 43 }; 44 45 /* Registers the RAS error record list with common RAS framework. */ 46 REGISTER_ERR_RECORD_INFO(plat_err_records); 47 /* Registers the RAS error interrupt info list with common RAS framework. */ 48 REGISTER_RAS_INTERRUPTS(plat_ras_interrupts); 49 50 /* Platform RAS handling config data definition */ 51 struct plat_nrd_ras_config ras_config = { 52 plat_ras_map, 53 ARRAY_SIZE(plat_ras_map) 54 }; 55