1 /*
2 * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <lib/utils_def.h>
12 #include <drivers/arm/css/sds.h>
13 #include <drivers/arm/sbsa.h>
14 #include <plat/arm/common/plat_arm.h>
15 #include <plat/common/platform.h>
16
17 #if SPM_MM
18 #include <services/spm_mm_partition.h>
19 #endif
20
21 /*
22 * Table of regions for different BL stages to map using the MMU.
23 */
24 #if IMAGE_BL1
25 const mmap_region_t plat_arm_mmap[] = {
26 NRD_CSS_SHARED_RAM_MMAP(0),
27 NRD_ROS_FLASH0_RO_MMAP,
28 NRD_CSS_PERIPH_MMAP(0),
29 NRD_ROS_PLATFORM_PERIPH_MMAP,
30 NRD_ROS_SYSTEM_PERIPH_MMAP,
31 {0}
32 };
33 #endif
34
35 #if IMAGE_BL2
36 const mmap_region_t plat_arm_mmap[] = {
37 NRD_CSS_SHARED_RAM_MMAP(0),
38 NRD_ROS_FLASH0_RO_MMAP,
39 #ifdef PLAT_ARM_MEM_PROT_ADDR
40 ARM_V2M_MAP_MEM_PROTECT,
41 #endif
42 NRD_CSS_PERIPH_MMAP(0),
43 NRD_ROS_MEMCNTRL_MMAP(0),
44 NRD_ROS_PLATFORM_PERIPH_MMAP,
45 NRD_ROS_SYSTEM_PERIPH_MMAP,
46 ARM_MAP_NS_DRAM1,
47 #if NRD_CHIP_COUNT > 1
48 NRD_ROS_MEMCNTRL_MMAP(1),
49 #endif
50 #if NRD_CHIP_COUNT > 2
51 NRD_ROS_MEMCNTRL_MMAP(2),
52 #endif
53 #if NRD_CHIP_COUNT > 3
54 NRD_ROS_MEMCNTRL_MMAP(3),
55 #endif
56 #if ARM_BL31_IN_DRAM
57 ARM_MAP_BL31_SEC_DRAM,
58 #endif
59 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
60 ARM_SP_IMAGE_MMAP,
61 #endif
62 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
63 ARM_MAP_BL1_RW,
64 #endif
65 {0}
66 };
67 #endif
68
69 #if IMAGE_BL31
70 const mmap_region_t plat_arm_mmap[] = {
71 NRD_CSS_SHARED_RAM_MMAP(0),
72 #ifdef PLAT_ARM_MEM_PROT_ADDR
73 ARM_V2M_MAP_MEM_PROTECT,
74 #endif
75 NRD_CSS_PERIPH_MMAP(0),
76 NRD_ROS_PLATFORM_PERIPH_MMAP,
77 NRD_ROS_SYSTEM_PERIPH_MMAP,
78 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
79 ARM_SPM_BUF_EL3_MMAP,
80 #endif
81 {0}
82 };
83
84 #if SPM_MM && defined(IMAGE_BL31)
85 const mmap_region_t plat_arm_secure_partition_mmap[] = {
86 NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
87 NRD_ROS_SECURE_NOR2_USER_MMAP,
88 NRD_CSS_SECURE_UART_USER_MMAP,
89 NRD_ROS_PLATFORM_PERIPH_USER_MMAP,
90 ARM_SP_IMAGE_MMAP,
91 ARM_SP_IMAGE_NS_BUF_MMAP,
92 #if ENABLE_FEAT_RAS && FFH_SUPPORT
93 NRD_CSS_SP_CPER_BUF_MMAP,
94 #endif
95 ARM_SP_IMAGE_RW_MMAP,
96 ARM_SPM_BUF_EL0_MMAP,
97 {0}
98 };
99 #endif /* SPM_MM && defined(IMAGE_BL31) */
100 #endif
101
102 ARM_CASSERT_MMAP
103
104 #if SPM_MM && defined(IMAGE_BL31)
105 /*
106 * Boot information passed to a secure partition during initialisation. Linear
107 * indices in MP information will be filled at runtime.
108 */
109 static spm_mm_mp_info_t sp_mp_info[] = {
110 [0] = {0x81000000, 0},
111 [1] = {0x81010000, 0},
112 [2] = {0x81020000, 0},
113 [3] = {0x81030000, 0},
114 [4] = {0x81040000, 0},
115 [5] = {0x81050000, 0},
116 [6] = {0x81060000, 0},
117 [7] = {0x81070000, 0},
118 [8] = {0x81080000, 0},
119 [9] = {0x81090000, 0},
120 [10] = {0x810a0000, 0},
121 [11] = {0x810b0000, 0},
122 [12] = {0x810c0000, 0},
123 [13] = {0x810d0000, 0},
124 [14] = {0x810e0000, 0},
125 [15] = {0x810f0000, 0},
126 };
127
128 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
129 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
130 .h.version = VERSION_1,
131 .h.size = sizeof(spm_mm_boot_info_t),
132 .h.attr = 0,
133 .sp_mem_base = ARM_SP_IMAGE_BASE,
134 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
135 .sp_image_base = ARM_SP_IMAGE_BASE,
136 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
137 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
138 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
139 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
140 .sp_image_size = ARM_SP_IMAGE_SIZE,
141 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
142 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
143 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
144 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
145 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
146 .num_cpus = PLATFORM_CORE_COUNT,
147 .mp_info = &sp_mp_info[0],
148 };
149
plat_get_secure_partition_mmap(void * cookie)150 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
151 {
152 return plat_arm_secure_partition_mmap;
153 }
154
plat_get_secure_partition_boot_info(void * cookie)155 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
156 void *cookie)
157 {
158 return &plat_arm_secure_partition_boot_info;
159 }
160 #endif /* SPM_MM && defined(IMAGE_BL31) */
161
162 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)163 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
164 {
165 assert(heap_addr != NULL);
166 assert(heap_size != NULL);
167
168 return arm_get_mbedtls_heap(heap_addr, heap_size);
169 }
170 #endif
171
plat_arm_secure_wdt_start(void)172 void plat_arm_secure_wdt_start(void)
173 {
174 sbsa_wdog_start(NRD_CSS_SECURE_WDOG_BASE, NRD_CSS_SECURE_WDOG_TIMEOUT);
175 }
176
plat_arm_secure_wdt_stop(void)177 void plat_arm_secure_wdt_stop(void)
178 {
179 sbsa_wdog_stop(NRD_CSS_SECURE_WDOG_BASE);
180 }
181
182 static sds_region_desc_t nrd_sds_regions[] = {
183 { .base = PLAT_ARM_SDS_MEM_BASE },
184 };
185
plat_sds_get_regions(unsigned int * region_count)186 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
187 {
188 *region_count = ARRAY_SIZE(nrd_sds_regions);
189
190 return nrd_sds_regions;
191 }
192