1*4ced5956SRohit Mathew# 2*4ced5956SRohit Mathew# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3*4ced5956SRohit Mathew# 4*4ced5956SRohit Mathew# SPDX-License-Identifier: BSD-3-Clause 5*4ced5956SRohit Mathew# 6*4ced5956SRohit Mathew 7*4ced5956SRohit MathewCSS_USE_SCMI_SDS_DRIVER := 1 8*4ced5956SRohit Mathew 9*4ced5956SRohit MathewNRD_COMMON_BASE := plat/arm/board/neoverse_rd/common 10*4ced5956SRohit Mathew 11*4ced5956SRohit MathewENABLE_FEAT_RAS := 1 12*4ced5956SRohit Mathew 13*4ced5956SRohit MathewSDEI_SUPPORT := 0 14*4ced5956SRohit Mathew 15*4ced5956SRohit MathewEL3_EXCEPTION_HANDLING := 0 16*4ced5956SRohit Mathew 17*4ced5956SRohit MathewHANDLE_EA_EL3_FIRST_NS := 0 18*4ced5956SRohit Mathew 19*4ced5956SRohit MathewCSS_SGI_CHIP_COUNT := 1 20*4ced5956SRohit Mathew 21*4ced5956SRohit MathewCSS_SGI_PLATFORM_VARIANT := 0 22*4ced5956SRohit Mathew 23*4ced5956SRohit Mathew# Do not enable SVE 24*4ced5956SRohit MathewENABLE_SVE_FOR_NS := 0 25*4ced5956SRohit Mathew 26*4ced5956SRohit MathewCTX_INCLUDE_FPREGS := 1 27*4ced5956SRohit Mathew 28*4ced5956SRohit MathewINTERCONNECT_SOURCES := ${NRD_COMMON_BASE}/nrd_interconnect.c 29*4ced5956SRohit Mathew 30*4ced5956SRohit MathewPLAT_INCLUDES += -I${NRD_COMMON_BASE}/include 31*4ced5956SRohit Mathew 32*4ced5956SRohit Mathew# GIC-600 configuration 33*4ced5956SRohit MathewGICV3_SUPPORT_GIC600 := 1 34*4ced5956SRohit Mathew 35*4ced5956SRohit Mathew# Include GICv3 driver files 36*4ced5956SRohit Mathewinclude drivers/arm/gic/v3/gicv3.mk 37*4ced5956SRohit Mathew 38*4ced5956SRohit MathewENT_GIC_SOURCES := ${GICV3_SOURCES} \ 39*4ced5956SRohit Mathew plat/common/plat_gicv3.c \ 40*4ced5956SRohit Mathew plat/arm/common/arm_gicv3.c 41*4ced5956SRohit Mathew 42*4ced5956SRohit MathewPLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/arch/aarch64/nrd_helper.S 43*4ced5956SRohit Mathew 44*4ced5956SRohit MathewBL1_SOURCES += ${INTERCONNECT_SOURCES} \ 45*4ced5956SRohit Mathew drivers/arm/sbsa/sbsa.c 46*4ced5956SRohit Mathew 47*4ced5956SRohit MathewBL2_SOURCES += ${NRD_COMMON_BASE}/nrd_image_load.c \ 48*4ced5956SRohit Mathew drivers/arm/css/sds/sds.c 49*4ced5956SRohit Mathew 50*4ced5956SRohit MathewBL31_SOURCES += ${INTERCONNECT_SOURCES} \ 51*4ced5956SRohit Mathew ${ENT_GIC_SOURCES} \ 52*4ced5956SRohit Mathew ${NRD_COMMON_BASE}/nrd_bl31_setup.c \ 53*4ced5956SRohit Mathew ${NRD_COMMON_BASE}/nrd_topology.c \ 54*4ced5956SRohit Mathew drivers/delay_timer/generic_delay_timer.c 55*4ced5956SRohit Mathew 56*4ced5956SRohit Mathewifneq (${RESET_TO_BL31},0) 57*4ced5956SRohit Mathew $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 58*4ced5956SRohit Mathew Please set RESET_TO_BL31 to 0.") 59*4ced5956SRohit Mathewendif 60*4ced5956SRohit Mathew 61*4ced5956SRohit Mathew$(eval $(call add_define,CSS_SGI_CHIP_COUNT)) 62*4ced5956SRohit Mathew 63*4ced5956SRohit Mathew$(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT)) 64*4ced5956SRohit Mathew 65*4ced5956SRohit Mathewoverride CSS_LOAD_SCP_IMAGES := 0 66*4ced5956SRohit Mathewoverride NEED_BL2U := no 67*4ced5956SRohit Mathewoverride ARM_PLAT_MT := 1 68*4ced5956SRohit Mathewoverride PSCI_EXTENDED_STATE_ID := 1 69*4ced5956SRohit Mathewoverride ARM_RECOM_STATE_ID_ENC := 1 70*4ced5956SRohit Mathew 71*4ced5956SRohit Mathew# System coherency is managed in hardware 72*4ced5956SRohit MathewHW_ASSISTED_COHERENCY := 1 73*4ced5956SRohit Mathew 74*4ced5956SRohit Mathew# When building for systems with hardware-assisted coherency, there's no need to 75*4ced5956SRohit Mathew# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 76*4ced5956SRohit MathewUSE_COHERENT_MEM := 0 77*4ced5956SRohit Mathew 78*4ced5956SRohit Mathewinclude plat/arm/common/arm_common.mk 79*4ced5956SRohit Mathewinclude plat/arm/css/common/css_common.mk 80*4ced5956SRohit Mathewinclude plat/arm/soc/common/soc_css.mk 81*4ced5956SRohit Mathewinclude plat/arm/board/common/board_common.mk 82