180d37c28SDeepak Pandey# 2*c5c54e20SBoyan Karatotev# Copyright (c) 2018-2025, Arm Limited. All rights reserved. 380d37c28SDeepak Pandey# 480d37c28SDeepak Pandey# SPDX-License-Identifier: BSD-3-Clause 580d37c28SDeepak Pandey# 680d37c28SDeepak Pandey 780d37c28SDeepak Pandey 880d37c28SDeepak PandeyN1SDP_BASE := plat/arm/board/n1sdp 980d37c28SDeepak Pandey 1080d37c28SDeepak PandeyPLAT_INCLUDES := -I${N1SDP_BASE}/include 1180d37c28SDeepak Pandey 1280d37c28SDeepak Pandey 13da6d75a0SJohn TsichritzisN1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S 1480d37c28SDeepak Pandey 15cf953bcaSGovindraj Raja# Neoverse N1 cores support Armv8.2 extensions 16cf953bcaSGovindraj RajaARM_ARCH_MAJOR := 8 17cf953bcaSGovindraj RajaARM_ARCH_MINOR := 2 18cf953bcaSGovindraj Raja 19a6ea06f5SAlexei Fedorov# GIC-600 configuration 20*c5c54e20SBoyan KaratotevUSE_GIC_DRIVER := 3 21b4ad365aSAndre PrzywaraGICV3_SUPPORT_GIC600 := 1 22a6ea06f5SAlexei FedorovGICV3_IMPL_GIC600_MULTICHIP := 1 2380d37c28SDeepak Pandey 2480d37c28SDeepak PandeyPLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \ 2580d37c28SDeepak Pandey ${N1SDP_BASE}/aarch64/n1sdp_helper.S 2680d37c28SDeepak Pandey 27fe2b37f6Ssah01BL1_SOURCES := ${N1SDP_CPU_SOURCES} \ 28fe2b37f6Ssah01 ${N1SDP_BASE}/n1sdp_err.c \ 29fe2b37f6Ssah01 ${N1SDP_BASE}/n1sdp_trusted_boot.c \ 30fe2b37f6Ssah01 ${N1SDP_BASE}/n1sdp_bl1_setup.c \ 31fe2b37f6Ssah01 drivers/arm/sbsa/sbsa.c 32fe2b37f6Ssah01 33fe2b37f6Ssah01BL2_SOURCES := ${N1SDP_BASE}/n1sdp_security.c \ 34fe2b37f6Ssah01 ${N1SDP_BASE}/n1sdp_err.c \ 35fe2b37f6Ssah01 ${N1SDP_BASE}/n1sdp_trusted_boot.c \ 36fe2b37f6Ssah01 lib/utils/mem_region.c \ 37fe2b37f6Ssah01 ${N1SDP_BASE}/n1sdp_bl2_setup.c \ 38cf85030eSsahil ${N1SDP_BASE}/n1sdp_image_load.c \ 39fe2b37f6Ssah01 drivers/arm/css/sds/sds.c 4080d37c28SDeepak Pandey 4180d37c28SDeepak PandeyBL31_SOURCES := ${N1SDP_CPU_SOURCES} \ 4280d37c28SDeepak Pandey ${N1SDP_BASE}/n1sdp_bl31_setup.c \ 435bdafc40SWerner Lewis ${N1SDP_BASE}/n1sdp_pm.c \ 4480d37c28SDeepak Pandey ${N1SDP_BASE}/n1sdp_topology.c \ 45de8bc83eSManoj Kumar ${N1SDP_BASE}/n1sdp_security.c \ 46de8bc83eSManoj Kumar drivers/arm/css/sds/sds.c 4780d37c28SDeepak Pandey 48000653b4SAndre PrzywaraFDT_SOURCES += fdts/${PLAT}-single-chip.dts \ 49fe2b37f6Ssah01 fdts/${PLAT}-multi-chip.dts \ 50fe2b37f6Ssah01 ${N1SDP_BASE}/fdts/n1sdp_fw_config.dts \ 51cf85030eSsahil ${N1SDP_BASE}/fdts/n1sdp_tb_fw_config.dts \ 52cf85030eSsahil ${N1SDP_BASE}/fdts/n1sdp_nt_fw_config.dts 53fe2b37f6Ssah01 54fe2b37f6Ssah01FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_fw_config.dtb 55fe2b37f6Ssah01TB_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_tb_fw_config.dtb 56cf85030eSsahilNT_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_nt_fw_config.dtb 57fe2b37f6Ssah01 58fe2b37f6Ssah01# Add the FW_CONFIG to FIP and specify the same to certtool 59fe2b37f6Ssah01$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 60fe2b37f6Ssah01# Add the TB_FW_CONFIG to FIP and specify the same to certtool 61fe2b37f6Ssah01$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 62cf85030eSsahil# Add the NT_FW_CONFIG to FIP and specify the same to certtool 63cf85030eSsahil$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG})) 64fe2b37f6Ssah01 659090fe00SVishnu BanavathN1SDP_SPMC_MANIFEST_DTS := ${N1SDP_BASE}/fdts/${PLAT}_optee_spmc_manifest.dts 669090fe00SVishnu BanavathFDT_SOURCES += ${N1SDP_SPMC_MANIFEST_DTS} 679090fe00SVishnu BanavathN1SDP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_optee_spmc_manifest.dtb 689090fe00SVishnu Banavath 699090fe00SVishnu Banavath# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 709090fe00SVishnu Banavath$(eval $(call TOOL_ADD_PAYLOAD,${N1SDP_TOS_FW_CONFIG},--tos-fw-config,${N1SDP_TOS_FW_CONFIG})) 719090fe00SVishnu Banavath 72fe2b37f6Ssah01# Setting to 0 as no NVCTR in N1SDP 73fe2b37f6Ssah01N1SDP_FW_NVCTR_VAL := 0 74fe2b37f6Ssah01TFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL} 75fe2b37f6Ssah01NTFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL} 76fe2b37f6Ssah01 77fe2b37f6Ssah01# Add N1SDP_FW_NVCTR_VAL 78fe2b37f6Ssah01$(eval $(call add_define,N1SDP_FW_NVCTR_VAL)) 7980d37c28SDeepak Pandey 8080d37c28SDeepak Pandey# TF-A not required to load the SCP Images 8180d37c28SDeepak Pandeyoverride CSS_LOAD_SCP_IMAGES := 0 8280d37c28SDeepak Pandey 8380d37c28SDeepak Pandeyoverride NEED_BL2U := no 8480d37c28SDeepak Pandey 8580d37c28SDeepak Pandey# 32 bit mode not supported 8680d37c28SDeepak Pandeyoverride CTX_INCLUDE_AARCH32_REGS := 0 8780d37c28SDeepak Pandey 8880d37c28SDeepak Pandeyoverride ARM_PLAT_MT := 1 8980d37c28SDeepak Pandey 9080d37c28SDeepak Pandey# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 9180d37c28SDeepak Pandey# SCP during power management operations and for SCP RAM Firmware transfer. 9280d37c28SDeepak PandeyCSS_USE_SCMI_SDS_DRIVER := 1 9380d37c28SDeepak Pandey 9480d37c28SDeepak Pandey# System coherency is managed in hardware 9580d37c28SDeepak PandeyHW_ASSISTED_COHERENCY := 1 9680d37c28SDeepak Pandey 9780d37c28SDeepak Pandey# When building for systems with hardware-assisted coherency, there's no need to 9880d37c28SDeepak Pandey# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 9980d37c28SDeepak PandeyUSE_COHERENT_MEM := 0 100303b6d06SChandni Cherukuri 101303b6d06SChandni Cherukuri# Enable the flag since N1SDP has a system level cache 10225bbbd2dSJavier Almansa SobrinoNEOVERSE_Nx_EXTERNAL_LLC := 1 10380d37c28SDeepak Pandeyinclude plat/arm/common/arm_common.mk 10480d37c28SDeepak Pandeyinclude plat/arm/css/common/css_common.mk 10580d37c28SDeepak Pandeyinclude plat/arm/board/common/board_common.mk 106