1de8bc83eSManoj Kumar /* 2de8bc83eSManoj Kumar * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3de8bc83eSManoj Kumar * 4de8bc83eSManoj Kumar * SPDX-License-Identifier: BSD-3-Clause 5de8bc83eSManoj Kumar */ 6de8bc83eSManoj Kumar 7de8bc83eSManoj Kumar #ifndef N1SDP_DEF_H 8de8bc83eSManoj Kumar #define N1SDP_DEF_H 9de8bc83eSManoj Kumar 10de8bc83eSManoj Kumar /* Non-secure SRAM MMU mapping */ 11de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_BASE (0x06000000) 12de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_SIZE (0x00010000) 13de8bc83eSManoj Kumar #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ 14de8bc83eSManoj Kumar N1SDP_NS_SRAM_BASE, \ 15de8bc83eSManoj Kumar N1SDP_NS_SRAM_SIZE, \ 16de8bc83eSManoj Kumar MT_DEVICE | MT_RW | MT_SECURE) 17de8bc83eSManoj Kumar 1834c7af41SManish Pandey /* SDS Platform information defines */ 1934c7af41SManish Pandey #define N1SDP_SDS_PLATFORM_INFO_STRUCT_ID 8 2034c7af41SManish Pandey #define N1SDP_SDS_PLATFORM_INFO_OFFSET 0 2134c7af41SManish Pandey #define N1SDP_SDS_PLATFORM_INFO_SIZE 4 2234c7af41SManish Pandey #define N1SDP_MAX_DDR_CAPACITY_GB 64 2334c7af41SManish Pandey #define N1SDP_MAX_SLAVE_COUNT 16 24de8bc83eSManoj Kumar 25de8bc83eSManoj Kumar /* SDS BL33 image information defines */ 26de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_STRUCT_ID 9 27de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_OFFSET 0 28de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_SIZE 12 29de8bc83eSManoj Kumar 307428bbf4SManoj Kumar /* DMC memory command registers */ 317428bbf4SManoj Kumar #define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008 327428bbf4SManoj Kumar #define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008 337428bbf4SManoj Kumar 34de8bc83eSManoj Kumar /* DMC ERR0CTLR0 registers */ 35de8bc83eSManoj Kumar #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 36de8bc83eSManoj Kumar #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 37de8bc83eSManoj Kumar 38*f91a8e4cSManish Pandey /* Remote DMC memory command registers */ 39*f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC0_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 40*f91a8e4cSManish Pandey N1SDP_DMC0_MEMC_CMD_REG 41*f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC1_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 42*f91a8e4cSManish Pandey N1SDP_DMC1_MEMC_CMD_REG 43*f91a8e4cSManish Pandey 44*f91a8e4cSManish Pandey /* Remote DMC ERR0CTLR0 registers */ 45*f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC0_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 46*f91a8e4cSManish Pandey N1SDP_DMC0_ERR0CTLR0_REG 47*f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC1_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 48*f91a8e4cSManish Pandey N1SDP_DMC1_ERR0CTLR0_REG 49*f91a8e4cSManish Pandey 507428bbf4SManoj Kumar /* DMC memory commands */ 517428bbf4SManoj Kumar #define N1SDP_DMC_MEMC_CMD_CONFIG 0 527428bbf4SManoj Kumar #define N1SDP_DMC_MEMC_CMD_READY 3 537428bbf4SManoj Kumar 54de8bc83eSManoj Kumar /* DMC ECC enable bit in ERR0CTLR0 register */ 55de8bc83eSManoj Kumar #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 56de8bc83eSManoj Kumar 5734c7af41SManish Pandey /* Base address of non-secure SRAM where Platform information will be filled */ 5834c7af41SManish Pandey #define N1SDP_PLATFORM_INFO_BASE 0x06008000 59de8bc83eSManoj Kumar 60de8bc83eSManoj Kumar #endif /* N1SDP_DEF_H */ 61