1*de8bc83eSManoj Kumar /* 2*de8bc83eSManoj Kumar * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*de8bc83eSManoj Kumar * 4*de8bc83eSManoj Kumar * SPDX-License-Identifier: BSD-3-Clause 5*de8bc83eSManoj Kumar */ 6*de8bc83eSManoj Kumar 7*de8bc83eSManoj Kumar #ifndef N1SDP_DEF_H 8*de8bc83eSManoj Kumar #define N1SDP_DEF_H 9*de8bc83eSManoj Kumar 10*de8bc83eSManoj Kumar /* Non-secure SRAM MMU mapping */ 11*de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_BASE (0x06000000) 12*de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_SIZE (0x00010000) 13*de8bc83eSManoj Kumar #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ 14*de8bc83eSManoj Kumar N1SDP_NS_SRAM_BASE, \ 15*de8bc83eSManoj Kumar N1SDP_NS_SRAM_SIZE, \ 16*de8bc83eSManoj Kumar MT_DEVICE | MT_RW | MT_SECURE) 17*de8bc83eSManoj Kumar 18*de8bc83eSManoj Kumar /* SDS memory information defines */ 19*de8bc83eSManoj Kumar #define N1SDP_SDS_MEM_INFO_STRUCT_ID 8 20*de8bc83eSManoj Kumar #define N1SDP_SDS_MEM_INFO_OFFSET 0 21*de8bc83eSManoj Kumar #define N1SDP_SDS_MEM_INFO_SIZE 4 22*de8bc83eSManoj Kumar 23*de8bc83eSManoj Kumar /* SDS BL33 image information defines */ 24*de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_STRUCT_ID 9 25*de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_OFFSET 0 26*de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_SIZE 12 27*de8bc83eSManoj Kumar 28*de8bc83eSManoj Kumar /* DMC ERR0CTLR0 registers */ 29*de8bc83eSManoj Kumar #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 30*de8bc83eSManoj Kumar #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 31*de8bc83eSManoj Kumar 32*de8bc83eSManoj Kumar /* DMC ECC enable bit in ERR0CTLR0 register */ 33*de8bc83eSManoj Kumar #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 34*de8bc83eSManoj Kumar 35*de8bc83eSManoj Kumar /* Base address of non-secure SRAM where DDR memory size will be filled */ 36*de8bc83eSManoj Kumar #define N1SDP_DDR_MEM_INFO_BASE 0x06008000 37*de8bc83eSManoj Kumar 38*de8bc83eSManoj Kumar #endif /* N1SDP_DEF_H */ 39