1de8bc83eSManoj Kumar /* 2de8bc83eSManoj Kumar * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3de8bc83eSManoj Kumar * 4de8bc83eSManoj Kumar * SPDX-License-Identifier: BSD-3-Clause 5de8bc83eSManoj Kumar */ 6de8bc83eSManoj Kumar 7de8bc83eSManoj Kumar #ifndef N1SDP_DEF_H 8de8bc83eSManoj Kumar #define N1SDP_DEF_H 9de8bc83eSManoj Kumar 10de8bc83eSManoj Kumar /* Non-secure SRAM MMU mapping */ 11de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_BASE (0x06000000) 12de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_SIZE (0x00010000) 13de8bc83eSManoj Kumar #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ 14de8bc83eSManoj Kumar N1SDP_NS_SRAM_BASE, \ 15de8bc83eSManoj Kumar N1SDP_NS_SRAM_SIZE, \ 16de8bc83eSManoj Kumar MT_DEVICE | MT_RW | MT_SECURE) 17de8bc83eSManoj Kumar 18de8bc83eSManoj Kumar /* SDS memory information defines */ 19de8bc83eSManoj Kumar #define N1SDP_SDS_MEM_INFO_STRUCT_ID 8 20de8bc83eSManoj Kumar #define N1SDP_SDS_MEM_INFO_OFFSET 0 21de8bc83eSManoj Kumar #define N1SDP_SDS_MEM_INFO_SIZE 4 22de8bc83eSManoj Kumar 23de8bc83eSManoj Kumar /* SDS BL33 image information defines */ 24de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_STRUCT_ID 9 25de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_OFFSET 0 26de8bc83eSManoj Kumar #define N1SDP_SDS_BL33_INFO_SIZE 12 27de8bc83eSManoj Kumar 28*7428bbf4SManoj Kumar /* DMC memory command registers */ 29*7428bbf4SManoj Kumar #define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008 30*7428bbf4SManoj Kumar #define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008 31*7428bbf4SManoj Kumar 32de8bc83eSManoj Kumar /* DMC ERR0CTLR0 registers */ 33de8bc83eSManoj Kumar #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 34de8bc83eSManoj Kumar #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 35de8bc83eSManoj Kumar 36*7428bbf4SManoj Kumar /* DMC memory commands */ 37*7428bbf4SManoj Kumar #define N1SDP_DMC_MEMC_CMD_CONFIG 0 38*7428bbf4SManoj Kumar #define N1SDP_DMC_MEMC_CMD_READY 3 39*7428bbf4SManoj Kumar 40de8bc83eSManoj Kumar /* DMC ECC enable bit in ERR0CTLR0 register */ 41de8bc83eSManoj Kumar #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 42de8bc83eSManoj Kumar 43de8bc83eSManoj Kumar /* Base address of non-secure SRAM where DDR memory size will be filled */ 44de8bc83eSManoj Kumar #define N1SDP_DDR_MEM_INFO_BASE 0x06008000 45de8bc83eSManoj Kumar 46de8bc83eSManoj Kumar #endif /* N1SDP_DEF_H */ 47