1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <drivers/arm/css/css_mhu_doorbell.h> 10 #include <drivers/arm/css/scmi.h> 11 #include <drivers/arm/css/sds.h> 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 #include <lib/utils.h> 15 #include <plat/arm/common/plat_arm.h> 16 17 #include "n1sdp_def.h" 18 19 /* 20 * Memory information structure stored in SDS. 21 * This structure holds the total DDR memory size which will be 22 * used when zeroing out the entire DDR memory before enabling 23 * the ECC capability in DMCs. 24 */ 25 struct n1sdp_mem_info { 26 uint32_t ddr_size_gb; 27 }; 28 29 /* 30 * BL33 image information structure stored in SDS. 31 * This structure holds the source & destination addresses and 32 * the size of the BL33 image which will be loaded by BL31. 33 */ 34 struct n1sdp_bl33_info { 35 uint32_t bl33_src_addr; 36 uint32_t bl33_dst_addr; 37 uint32_t bl33_size; 38 }; 39 40 static scmi_channel_plat_info_t n1sdp_scmi_plat_info = { 41 .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE, 42 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, 43 .db_preserve_mask = 0xfffffffe, 44 .db_modify_mask = 0x1, 45 .ring_doorbell = &mhu_ring_doorbell, 46 }; 47 48 scmi_channel_plat_info_t *plat_css_get_scmi_info() 49 { 50 return &n1sdp_scmi_plat_info; 51 } 52 53 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 54 { 55 return css_scmi_override_pm_ops(ops); 56 } 57 58 /* 59 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC 60 * capability, the entire DDR memory space has to be zeroed out before 61 * enabling the ECC bits in DMC620. Zeroing out several gigabytes of 62 * memory from SCP is quite time consuming so the following function 63 * is added to zero out the DDR memory from application processor which is 64 * much faster compared to SCP. BL33 binary cannot be copied to DDR memory 65 * before enabling ECC so copy_bl33 function is added to copy BL33 binary 66 * from IOFPGA-DDR3 memory to main DDR4 memory. 67 */ 68 69 void dmc_ecc_setup(uint32_t ddr_size_gb) 70 { 71 uint64_t dram2_size; 72 73 dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) - 74 ARM_DRAM1_SIZE; 75 76 INFO("Zeroing DDR memories\n"); 77 zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); 78 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); 79 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); 80 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); 81 82 INFO("Enabling ECC on DMCs\n"); 83 mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); 84 mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); 85 } 86 87 void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) 88 { 89 uint32_t i; 90 91 INFO("Copying BL33 to DDR memory\n"); 92 for (i = 0; i < size; i = i + 8) 93 mmio_write_64((dst + i), mmio_read_64(src + i)); 94 95 for (i = 0; i < size; i = i + 8) { 96 if (mmio_read_64(src + i) != mmio_read_64(dst + i)) { 97 ERROR("Copy failed!\n"); 98 panic(); 99 } 100 } 101 } 102 103 void bl31_platform_setup(void) 104 { 105 int ret; 106 struct n1sdp_mem_info mem_info; 107 struct n1sdp_bl33_info bl33_info; 108 109 arm_bl31_platform_setup(); 110 111 ret = sds_init(); 112 if (ret != SDS_OK) { 113 ERROR("SDS initialization failed\n"); 114 panic(); 115 } 116 117 ret = sds_struct_read(N1SDP_SDS_MEM_INFO_STRUCT_ID, 118 N1SDP_SDS_MEM_INFO_OFFSET, 119 &mem_info, 120 N1SDP_SDS_MEM_INFO_SIZE, 121 SDS_ACCESS_MODE_NON_CACHED); 122 if (ret != SDS_OK) { 123 ERROR("Error getting memory info from SDS\n"); 124 panic(); 125 } 126 dmc_ecc_setup(mem_info.ddr_size_gb); 127 128 ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID, 129 N1SDP_SDS_BL33_INFO_OFFSET, 130 &bl33_info, 131 N1SDP_SDS_BL33_INFO_SIZE, 132 SDS_ACCESS_MODE_NON_CACHED); 133 if (ret != SDS_OK) { 134 ERROR("Error getting BL33 info from SDS\n"); 135 panic(); 136 } 137 copy_bl33(bl33_info.bl33_src_addr, 138 bl33_info.bl33_dst_addr, 139 bl33_info.bl33_size); 140 /* 141 * Pass DDR memory size info to BL33. This method is followed as 142 * currently there is no BL1/BL2 involved in boot flow of N1SDP. 143 * When TBBR is implemented for N1SDP, this method should be removed 144 * and DDR memory size shoule be passed to BL33 using NT_FW_CONFIG 145 * passing mechanism. 146 */ 147 mmio_write_32(N1SDP_DDR_MEM_INFO_BASE, mem_info.ddr_size_gb); 148 } 149