1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arm_def.h> 11 #include <board_css_def.h> 12 #include <css_def.h> 13 14 #if CSS_USE_SCMI_SDS_DRIVER 15 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 16 #else 17 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 18 #endif 19 20 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 21 #define PLAT_ARM_MAX_BL31_SIZE 0X20000 22 23 24 /******************************************************************************* 25 * N1SDP topology related constants 26 ******************************************************************************/ 27 #define N1SDP_MAX_CPUS_PER_CLUSTER 2 28 #define PLAT_ARM_CLUSTER_COUNT 2 29 #define N1SDP_MAX_PE_PER_CPU 1 30 31 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 32 N1SDP_MAX_CPUS_PER_CLUSTER * \ 33 N1SDP_MAX_PE_PER_CPU) 34 35 36 /* 37 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 38 * plat_arm_mmap array defined for each BL stage. 39 */ 40 #define PLAT_ARM_MMAP_ENTRIES 3 41 #define MAX_XLAT_TABLES 4 42 43 #define PLATFORM_STACK_SIZE 0x400 44 45 #define PLAT_ARM_NSTIMER_FRAME_ID 0 46 #define PLAT_CSS_MHU_BASE 0x45000000 47 #define PLAT_MAX_PWR_LVL 1 48 49 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 50 CSS_IRQ_MHU 51 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 52 53 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 54 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 55 56 57 #define N1SDP_DEVICE_BASE (0x20000000) 58 #define N1SDP_DEVICE_SIZE (0x20000000) 59 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 60 N1SDP_DEVICE_BASE, \ 61 N1SDP_DEVICE_SIZE, \ 62 MT_DEVICE | MT_RW | MT_SECURE) 63 64 /* GIC related constants */ 65 #define PLAT_ARM_GICD_BASE 0x30000000 66 #define PLAT_ARM_GICC_BASE 0x2C000000 67 #define PLAT_ARM_GICR_BASE 0x300C0000 68 69 /* Platform ID address */ 70 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 71 #endif /* __PLATFORM_DEF_H__ */ 72