1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arm_def.h> 11 #include <css_def.h> 12 13 /* UART related constants */ 14 #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 15 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 16 17 #define PLAT_ARM_BL31_RUN_UART_BASE 0x2A410000 18 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 50000000 19 20 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 21 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 22 23 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 24 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 25 26 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) 27 28 #if CSS_USE_SCMI_SDS_DRIVER 29 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 30 #else 31 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 32 #endif 33 34 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 35 #define PLAT_ARM_MAX_BL31_SIZE 0X20000 36 37 38 /******************************************************************************* 39 * N1SDP topology related constants 40 ******************************************************************************/ 41 #define N1SDP_MAX_CPUS_PER_CLUSTER 2 42 #define PLAT_ARM_CLUSTER_COUNT 2 43 #define N1SDP_MAX_PE_PER_CPU 1 44 45 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 46 N1SDP_MAX_CPUS_PER_CLUSTER * \ 47 N1SDP_MAX_PE_PER_CPU) 48 49 /* System power domain level */ 50 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 51 52 /* 53 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 54 * plat_arm_mmap array defined for each BL stage. 55 */ 56 #define PLAT_ARM_MMAP_ENTRIES 3 57 #define MAX_XLAT_TABLES 4 58 59 #define PLATFORM_STACK_SIZE 0x400 60 61 #define PLAT_ARM_NSTIMER_FRAME_ID 0 62 #define PLAT_CSS_MHU_BASE 0x45000000 63 #define PLAT_MAX_PWR_LVL 1 64 65 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 66 CSS_IRQ_MHU 67 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 68 69 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 70 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 71 72 73 #define N1SDP_DEVICE_BASE (0x20000000) 74 #define N1SDP_DEVICE_SIZE (0x30000000) 75 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 76 N1SDP_DEVICE_BASE, \ 77 N1SDP_DEVICE_SIZE, \ 78 MT_DEVICE | MT_RW | MT_SECURE) 79 80 /* GIC related constants */ 81 #define PLAT_ARM_GICD_BASE 0x30000000 82 #define PLAT_ARM_GICC_BASE 0x2C000000 83 #define PLAT_ARM_GICR_BASE 0x300C0000 84 85 /* Platform ID address */ 86 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 87 88 #endif /* PLATFORM_DEF_H */ 89