1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 17 18 #define PLAT_ARM_RUN_UART_BASE 0x2A410000 19 #define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000 20 21 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 22 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 23 24 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 25 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 26 27 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 28 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) 29 30 /* 31 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC 32 * capability, the entire DDR memory space has to be zeroed out before 33 * enabling the ECC bits in DMC620. The access the complete DDR memory 34 * space the physical & virtual address space limits are extended to 35 * 40-bits. 36 */ 37 #ifndef AARCH32 38 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) 39 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) 40 #else 41 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 42 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 43 #endif 44 45 #if CSS_USE_SCMI_SDS_DRIVER 46 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 47 #else 48 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 49 #endif 50 51 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 52 #define PLAT_ARM_MAX_BL31_SIZE 0X20000 53 54 55 /******************************************************************************* 56 * N1SDP topology related constants 57 ******************************************************************************/ 58 #define N1SDP_MAX_CPUS_PER_CLUSTER 2 59 #define PLAT_ARM_CLUSTER_COUNT 2 60 #define N1SDP_MAX_PE_PER_CPU 1 61 62 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 63 N1SDP_MAX_CPUS_PER_CLUSTER * \ 64 N1SDP_MAX_PE_PER_CPU) 65 66 /* System power domain level */ 67 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 68 69 /* 70 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 71 * plat_arm_mmap array defined for each BL stage. 72 */ 73 #define PLAT_ARM_MMAP_ENTRIES 6 74 #define MAX_XLAT_TABLES 7 75 76 #define PLATFORM_STACK_SIZE 0x400 77 78 #define PLAT_ARM_NSTIMER_FRAME_ID 0 79 #define PLAT_CSS_MHU_BASE 0x45000000 80 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 81 #define PLAT_MAX_PWR_LVL 1 82 83 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 84 CSS_IRQ_MHU 85 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 86 87 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 88 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 89 90 91 #define N1SDP_DEVICE_BASE (0x08000000) 92 #define N1SDP_DEVICE_SIZE (0x48000000) 93 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 94 N1SDP_DEVICE_BASE, \ 95 N1SDP_DEVICE_SIZE, \ 96 MT_DEVICE | MT_RW | MT_SECURE) 97 98 #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ 99 ARM_DRAM1_BASE, \ 100 ARM_DRAM1_SIZE, \ 101 MT_MEMORY | MT_RW | MT_NS) 102 103 /* GIC related constants */ 104 #define PLAT_ARM_GICD_BASE 0x30000000 105 #define PLAT_ARM_GICC_BASE 0x2C000000 106 #define PLAT_ARM_GICR_BASE 0x300C0000 107 108 /* Platform ID address */ 109 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 110 111 /* Secure Watchdog Constants */ 112 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 113 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 114 115 #endif /* PLATFORM_DEF_H */ 116