1# 2# Copyright (c) 2020, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7MORELLO_BASE := plat/arm/board/morello 8 9INTERCONNECT_SOURCES := ${MORELLO_BASE}/morello_interconnect.c 10 11PLAT_INCLUDES := -I${MORELLO_BASE}/include 12 13MORELLO_CPU_SOURCES := lib/cpus/aarch64/rainier.S 14 15MORELLO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 16 drivers/arm/gic/v3/gicv3_main.c \ 17 drivers/arm/gic/v3/gicv3_helpers.c \ 18 plat/common/plat_gicv3.c \ 19 plat/arm/common/arm_gicv3.c \ 20 drivers/arm/gic/v3/gic600.c 21 22PLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \ 23 ${MORELLO_BASE}/aarch64/morello_helper.S 24 25BL31_SOURCES := ${MORELLO_CPU_SOURCES} \ 26 ${INTERCONNECT_SOURCES} \ 27 ${MORELLO_GIC_SOURCES} \ 28 ${MORELLO_BASE}/morello_bl31_setup.c \ 29 ${MORELLO_BASE}/morello_topology.c \ 30 ${MORELLO_BASE}/morello_security.c \ 31 drivers/arm/css/sds/sds.c 32 33FDT_SOURCES += fdts/morello-fvp.dts 34 35# TF-A not required to load the SCP Images 36override CSS_LOAD_SCP_IMAGES := 0 37 38# BL1/BL2 Image not a part of the capsule Image for morello 39override NEED_BL1 := no 40override NEED_BL2 := no 41override NEED_BL2U := no 42 43#TF-A for morello starts from BL31 44override RESET_TO_BL31 := 1 45 46# 32 bit mode not supported 47override CTX_INCLUDE_AARCH32_REGS := 0 48 49override ARM_PLAT_MT := 1 50 51# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 52# SCP during power management operations and for SCP RAM Firmware transfer. 53CSS_USE_SCMI_SDS_DRIVER := 1 54 55# System coherency is managed in hardware 56HW_ASSISTED_COHERENCY := 1 57 58# When building for systems with hardware-assisted coherency, there's no need to 59# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 60USE_COHERENT_MEM := 0 61 62include plat/arm/common/arm_common.mk 63include plat/arm/css/common/css_common.mk 64include plat/arm/board/common/board_common.mk 65 66override ERRATA_N1_1542419 := 1 67