1*dfd5bfb0SChandni Cherukuri# 2*dfd5bfb0SChandni Cherukuri# Copyright (c) 2020, Arm Limited. All rights reserved. 3*dfd5bfb0SChandni Cherukuri# 4*dfd5bfb0SChandni Cherukuri# SPDX-License-Identifier: BSD-3-Clause 5*dfd5bfb0SChandni Cherukuri# 6*dfd5bfb0SChandni Cherukuri 7*dfd5bfb0SChandni CherukuriMORELLO_BASE := plat/arm/board/morello 8*dfd5bfb0SChandni Cherukuri 9*dfd5bfb0SChandni CherukuriINTERCONNECT_SOURCES := ${MORELLO_BASE}/morello_interconnect.c 10*dfd5bfb0SChandni Cherukuri 11*dfd5bfb0SChandni CherukuriPLAT_INCLUDES := -I${MORELLO_BASE}/include 12*dfd5bfb0SChandni Cherukuri 13*dfd5bfb0SChandni CherukuriMORELLO_CPU_SOURCES := lib/cpus/aarch64/rainier.S 14*dfd5bfb0SChandni Cherukuri 15*dfd5bfb0SChandni CherukuriMORELLO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 16*dfd5bfb0SChandni Cherukuri drivers/arm/gic/v3/gicv3_main.c \ 17*dfd5bfb0SChandni Cherukuri drivers/arm/gic/v3/gicv3_helpers.c \ 18*dfd5bfb0SChandni Cherukuri plat/common/plat_gicv3.c \ 19*dfd5bfb0SChandni Cherukuri plat/arm/common/arm_gicv3.c \ 20*dfd5bfb0SChandni Cherukuri drivers/arm/gic/v3/gic600.c 21*dfd5bfb0SChandni Cherukuri 22*dfd5bfb0SChandni CherukuriPLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \ 23*dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/aarch64/morello_helper.S 24*dfd5bfb0SChandni Cherukuri 25*dfd5bfb0SChandni CherukuriBL31_SOURCES := ${MORELLO_CPU_SOURCES} \ 26*dfd5bfb0SChandni Cherukuri ${INTERCONNECT_SOURCES} \ 27*dfd5bfb0SChandni Cherukuri ${MORELLO_GIC_SOURCES} \ 28*dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/morello_bl31_setup.c \ 29*dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/morello_topology.c \ 30*dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/morello_security.c \ 31*dfd5bfb0SChandni Cherukuri drivers/arm/css/sds/sds.c 32*dfd5bfb0SChandni Cherukuri 33*dfd5bfb0SChandni CherukuriFDT_SOURCES += fdts/morello-fvp.dts 34*dfd5bfb0SChandni Cherukuri 35*dfd5bfb0SChandni Cherukuri# TF-A not required to load the SCP Images 36*dfd5bfb0SChandni Cherukurioverride CSS_LOAD_SCP_IMAGES := 0 37*dfd5bfb0SChandni Cherukuri 38*dfd5bfb0SChandni Cherukuri# BL1/BL2 Image not a part of the capsule Image for morello 39*dfd5bfb0SChandni Cherukurioverride NEED_BL1 := no 40*dfd5bfb0SChandni Cherukurioverride NEED_BL2 := no 41*dfd5bfb0SChandni Cherukurioverride NEED_BL2U := no 42*dfd5bfb0SChandni Cherukuri 43*dfd5bfb0SChandni Cherukuri#TF-A for morello starts from BL31 44*dfd5bfb0SChandni Cherukurioverride RESET_TO_BL31 := 1 45*dfd5bfb0SChandni Cherukuri 46*dfd5bfb0SChandni Cherukuri# 32 bit mode not supported 47*dfd5bfb0SChandni Cherukurioverride CTX_INCLUDE_AARCH32_REGS := 0 48*dfd5bfb0SChandni Cherukuri 49*dfd5bfb0SChandni Cherukurioverride ARM_PLAT_MT := 1 50*dfd5bfb0SChandni Cherukuri 51*dfd5bfb0SChandni Cherukuri# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 52*dfd5bfb0SChandni Cherukuri# SCP during power management operations and for SCP RAM Firmware transfer. 53*dfd5bfb0SChandni CherukuriCSS_USE_SCMI_SDS_DRIVER := 1 54*dfd5bfb0SChandni Cherukuri 55*dfd5bfb0SChandni Cherukuri# System coherency is managed in hardware 56*dfd5bfb0SChandni CherukuriHW_ASSISTED_COHERENCY := 1 57*dfd5bfb0SChandni Cherukuri 58*dfd5bfb0SChandni Cherukuri# When building for systems with hardware-assisted coherency, there's no need to 59*dfd5bfb0SChandni Cherukuri# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 60*dfd5bfb0SChandni CherukuriUSE_COHERENT_MEM := 0 61*dfd5bfb0SChandni Cherukuri 62*dfd5bfb0SChandni Cherukuriinclude plat/arm/common/arm_common.mk 63*dfd5bfb0SChandni Cherukuriinclude plat/arm/css/common/css_common.mk 64*dfd5bfb0SChandni Cherukuriinclude plat/arm/board/common/board_common.mk 65*dfd5bfb0SChandni Cherukuri 66*dfd5bfb0SChandni Cherukurioverride ERRATA_N1_1542419 := 1 67