1dfd5bfb0SChandni Cherukuri# 2dfd5bfb0SChandni Cherukuri# Copyright (c) 2020, Arm Limited. All rights reserved. 3dfd5bfb0SChandni Cherukuri# 4dfd5bfb0SChandni Cherukuri# SPDX-License-Identifier: BSD-3-Clause 5dfd5bfb0SChandni Cherukuri# 6dfd5bfb0SChandni Cherukuri 7dfd5bfb0SChandni CherukuriMORELLO_BASE := plat/arm/board/morello 8dfd5bfb0SChandni Cherukuri 9dfd5bfb0SChandni CherukuriINTERCONNECT_SOURCES := ${MORELLO_BASE}/morello_interconnect.c 10dfd5bfb0SChandni Cherukuri 11dfd5bfb0SChandni CherukuriPLAT_INCLUDES := -I${MORELLO_BASE}/include 12dfd5bfb0SChandni Cherukuri 13dfd5bfb0SChandni CherukuriMORELLO_CPU_SOURCES := lib/cpus/aarch64/rainier.S 14dfd5bfb0SChandni Cherukuri 15*6c07a927SChandni Cherukuri# GIC-600 configuration 16*6c07a927SChandni CherukuriGICV3_SUPPORT_GIC600 := 1 17*6c07a927SChandni Cherukuri 18*6c07a927SChandni Cherukuri# Include GICv3 driver files 19*6c07a927SChandni Cherukuriinclude drivers/arm/gic/v3/gicv3.mk 20*6c07a927SChandni Cherukuri 21*6c07a927SChandni CherukuriMORELLO_GIC_SOURCES := ${GICV3_SOURCES} \ 22dfd5bfb0SChandni Cherukuri plat/common/plat_gicv3.c \ 23dfd5bfb0SChandni Cherukuri plat/arm/common/arm_gicv3.c \ 24dfd5bfb0SChandni Cherukuri 25dfd5bfb0SChandni CherukuriPLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \ 26dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/aarch64/morello_helper.S 27dfd5bfb0SChandni Cherukuri 28dfd5bfb0SChandni CherukuriBL31_SOURCES := ${MORELLO_CPU_SOURCES} \ 29dfd5bfb0SChandni Cherukuri ${INTERCONNECT_SOURCES} \ 30dfd5bfb0SChandni Cherukuri ${MORELLO_GIC_SOURCES} \ 31dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/morello_bl31_setup.c \ 32dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/morello_topology.c \ 33dfd5bfb0SChandni Cherukuri ${MORELLO_BASE}/morello_security.c \ 34dfd5bfb0SChandni Cherukuri drivers/arm/css/sds/sds.c 35dfd5bfb0SChandni Cherukuri 36dfd5bfb0SChandni CherukuriFDT_SOURCES += fdts/morello-fvp.dts 37dfd5bfb0SChandni Cherukuri 38dfd5bfb0SChandni Cherukuri# TF-A not required to load the SCP Images 39dfd5bfb0SChandni Cherukurioverride CSS_LOAD_SCP_IMAGES := 0 40dfd5bfb0SChandni Cherukuri 41dfd5bfb0SChandni Cherukuri# BL1/BL2 Image not a part of the capsule Image for morello 42dfd5bfb0SChandni Cherukurioverride NEED_BL1 := no 43dfd5bfb0SChandni Cherukurioverride NEED_BL2 := no 44dfd5bfb0SChandni Cherukurioverride NEED_BL2U := no 45dfd5bfb0SChandni Cherukuri 46dfd5bfb0SChandni Cherukuri#TF-A for morello starts from BL31 47dfd5bfb0SChandni Cherukurioverride RESET_TO_BL31 := 1 48dfd5bfb0SChandni Cherukuri 49dfd5bfb0SChandni Cherukuri# 32 bit mode not supported 50dfd5bfb0SChandni Cherukurioverride CTX_INCLUDE_AARCH32_REGS := 0 51dfd5bfb0SChandni Cherukuri 52dfd5bfb0SChandni Cherukurioverride ARM_PLAT_MT := 1 53dfd5bfb0SChandni Cherukuri 54dfd5bfb0SChandni Cherukuri# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 55dfd5bfb0SChandni Cherukuri# SCP during power management operations and for SCP RAM Firmware transfer. 56dfd5bfb0SChandni CherukuriCSS_USE_SCMI_SDS_DRIVER := 1 57dfd5bfb0SChandni Cherukuri 58dfd5bfb0SChandni Cherukuri# System coherency is managed in hardware 59dfd5bfb0SChandni CherukuriHW_ASSISTED_COHERENCY := 1 60dfd5bfb0SChandni Cherukuri 61dfd5bfb0SChandni Cherukuri# When building for systems with hardware-assisted coherency, there's no need to 62dfd5bfb0SChandni Cherukuri# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 63dfd5bfb0SChandni CherukuriUSE_COHERENT_MEM := 0 64dfd5bfb0SChandni Cherukuri 65dfd5bfb0SChandni Cherukuriinclude plat/arm/common/arm_common.mk 66dfd5bfb0SChandni Cherukuriinclude plat/arm/css/common/css_common.mk 67dfd5bfb0SChandni Cherukuriinclude plat/arm/board/common/board_common.mk 68dfd5bfb0SChandni Cherukuri 69dfd5bfb0SChandni Cherukurioverride ERRATA_N1_1542419 := 1 70