1 /* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MORELLO_DEF_H 8 #define MORELLO_DEF_H 9 10 /* Non-secure SRAM MMU mapping */ 11 #define MORELLO_NS_SRAM_BASE UL(0x06000000) 12 #define MORELLO_NS_SRAM_SIZE UL(0x00010000) 13 #define MORELLO_MAP_NS_SRAM MAP_REGION_FLAT( \ 14 MORELLO_NS_SRAM_BASE, \ 15 MORELLO_NS_SRAM_SIZE, \ 16 MT_DEVICE | MT_RW | MT_SECURE) 17 18 /* SDS Platform information defines */ 19 #define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8) 20 #define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0) 21 #define MORELLO_SDS_PLATFORM_INFO_SIZE U(22) 22 #define MORELLO_MAX_DDR_CAPACITY U(0x1000000000) 23 #define MORELLO_MAX_SLAVE_COUNT U(16) 24 25 /* SDS BL33 image information defines */ 26 #define MORELLO_SDS_BL33_INFO_STRUCT_ID U(9) 27 #define MORELLO_SDS_BL33_INFO_OFFSET U(0) 28 #define MORELLO_SDS_BL33_INFO_SIZE U(12) 29 30 #define MORELLO_SCC_SERVER_MODE U(0) 31 #define MORELLO_SCC_CLIENT_MODE_MASK U(1) 32 #define MORELLO_SCC_C1_TAG_CACHE_EN_MASK U(4) 33 #define MORELLO_SCC_C2_TAG_CACHE_EN_MASK U(8) 34 35 /* Base address of non-secure SRAM where Platform information will be filled */ 36 #define MORELLO_PLATFORM_INFO_BASE UL(0x06000000) 37 38 /* DMC memory status registers */ 39 #define MORELLO_DMC0_MEMC_STATUS_REG UL(0x4E000000) 40 #define MORELLO_DMC1_MEMC_STATUS_REG UL(0x4E100000) 41 42 #define MORELLO_DMC_MEMC_STATUS_MASK U(7) 43 44 /* DMC memory command registers */ 45 #define MORELLO_DMC0_MEMC_CMD_REG UL(0x4E000008) 46 #define MORELLO_DMC1_MEMC_CMD_REG UL(0x4E100008) 47 48 /* DMC capability control register */ 49 #define MORELLO_DMC0_CAP_CTRL_REG UL(0x4E000D00) 50 #define MORELLO_DMC1_CAP_CTRL_REG UL(0x4E100D00) 51 52 /* DMC tag cache control register */ 53 #define MORELLO_DMC0_TAG_CACHE_CTL UL(0x4E000D04) 54 #define MORELLO_DMC1_TAG_CACHE_CTL UL(0x4E100D04) 55 56 /* DMC tag cache config register */ 57 #define MORELLO_DMC0_TAG_CACHE_CFG UL(0x4E000D08) 58 #define MORELLO_DMC1_TAG_CACHE_CFG UL(0x4E100D08) 59 60 /* DMC memory access control register */ 61 #define MORELLO_DMC0_MEM_ACCESS_CTL UL(0x4E000D0C) 62 #define MORELLO_DMC1_MEM_ACCESS_CTL UL(0x4E100D0C) 63 64 #define MORELLO_DMC_MEM_ACCESS_DIS (1UL << 16) 65 66 /* DMC memory address control register */ 67 #define MORELLO_DMC0_MEM_ADDR_CTL UL(0x4E000D10) 68 #define MORELLO_DMC1_MEM_ADDR_CTL UL(0x4E100D10) 69 70 /* DMC memory address control 2 register */ 71 #define MORELLO_DMC0_MEM_ADDR_CTL2 UL(0x4E000D14) 72 #define MORELLO_DMC1_MEM_ADDR_CTL2 UL(0x4E100D14) 73 74 /* DMC special control register */ 75 #define MORELLO_DMC0_SPL_CTL_REG UL(0x4E000D18) 76 #define MORELLO_DMC1_SPL_CTL_REG UL(0x4E100D18) 77 78 /* DMC ERR0CTLR0 registers */ 79 #define MORELLO_DMC0_ERR0CTLR0_REG UL(0x4E000708) 80 #define MORELLO_DMC1_ERR0CTLR0_REG UL(0x4E100708) 81 82 /* DMC ECC in ERR0CTLR0 register */ 83 #define MORELLO_DMC_ERR0CTLR0_ECC_EN U(9) 84 85 /* DMC ERR2STATUS register */ 86 #define MORELLO_DMC0_ERR2STATUS_REG UL(0x4E000790) 87 #define MORELLO_DMC1_ERR2STATUS_REG UL(0x4E100790) 88 89 /* DMC memory commands */ 90 #define MORELLO_DMC_MEMC_CMD_CONFIG U(0) 91 #define MORELLO_DMC_MEMC_CMD_READY U(3) 92 93 #endif /* MORELLO_DEF_H */ 94