1 /* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MORELLO_DEF_H 8 #define MORELLO_DEF_H 9 10 /* Non-secure SRAM MMU mapping */ 11 #define MORELLO_NS_SRAM_BASE UL(0x06000000) 12 #define MORELLO_NS_SRAM_SIZE UL(0x00010000) 13 #define MORELLO_MAP_NS_SRAM MAP_REGION_FLAT( \ 14 MORELLO_NS_SRAM_BASE, \ 15 MORELLO_NS_SRAM_SIZE, \ 16 MT_DEVICE | MT_RW | MT_SECURE) 17 18 /* SDS Platform information defines */ 19 #define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8) 20 #define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0) 21 #define MORELLO_SDS_PLATFORM_INFO_SIZE U(22) 22 #define MORELLO_MAX_DDR_CAPACITY U(0x1000000000) 23 #define MORELLO_MAX_SLAVE_COUNT U(16) 24 25 #define MORELLO_SCC_SERVER_MODE U(0) 26 #define MORELLO_SCC_CLIENT_MODE_MASK U(1) 27 #define MORELLO_SCC_C1_TAG_CACHE_EN_MASK U(4) 28 #define MORELLO_SCC_C2_TAG_CACHE_EN_MASK U(8) 29 30 /* Base address of non-secure SRAM where Platform information will be filled */ 31 #define MORELLO_PLATFORM_INFO_BASE UL(0x06000000) 32 33 /* DMC memory status registers */ 34 #define MORELLO_DMC0_MEMC_STATUS_REG UL(0x4E000000) 35 #define MORELLO_DMC1_MEMC_STATUS_REG UL(0x4E100000) 36 37 #define MORELLO_DMC_MEMC_STATUS_MASK U(7) 38 39 /* DMC memory command registers */ 40 #define MORELLO_DMC0_MEMC_CMD_REG UL(0x4E000008) 41 #define MORELLO_DMC1_MEMC_CMD_REG UL(0x4E100008) 42 43 /* DMC capability control register */ 44 #define MORELLO_DMC0_CAP_CTRL_REG UL(0x4E000D00) 45 #define MORELLO_DMC1_CAP_CTRL_REG UL(0x4E100D00) 46 47 /* DMC tag cache control register */ 48 #define MORELLO_DMC0_TAG_CACHE_CTL UL(0x4E000D04) 49 #define MORELLO_DMC1_TAG_CACHE_CTL UL(0x4E100D04) 50 51 /* DMC tag cache config register */ 52 #define MORELLO_DMC0_TAG_CACHE_CFG UL(0x4E000D08) 53 #define MORELLO_DMC1_TAG_CACHE_CFG UL(0x4E100D08) 54 55 /* DMC memory access control register */ 56 #define MORELLO_DMC0_MEM_ACCESS_CTL UL(0x4E000D0C) 57 #define MORELLO_DMC1_MEM_ACCESS_CTL UL(0x4E100D0C) 58 59 #define MORELLO_DMC_MEM_ACCESS_DIS (1UL << 16) 60 61 /* DMC memory address control register */ 62 #define MORELLO_DMC0_MEM_ADDR_CTL UL(0x4E000D10) 63 #define MORELLO_DMC1_MEM_ADDR_CTL UL(0x4E100D10) 64 65 /* DMC memory address control 2 register */ 66 #define MORELLO_DMC0_MEM_ADDR_CTL2 UL(0x4E000D14) 67 #define MORELLO_DMC1_MEM_ADDR_CTL2 UL(0x4E100D14) 68 69 /* DMC special control register */ 70 #define MORELLO_DMC0_SPL_CTL_REG UL(0x4E000D18) 71 #define MORELLO_DMC1_SPL_CTL_REG UL(0x4E100D18) 72 73 /* DMC ERR0CTLR0 registers */ 74 #define MORELLO_DMC0_ERR0CTLR0_REG UL(0x4E000708) 75 #define MORELLO_DMC1_ERR0CTLR0_REG UL(0x4E100708) 76 77 /* DMC ECC in ERR0CTLR0 register */ 78 #define MORELLO_DMC_ERR0CTLR0_ECC_EN U(9) 79 80 /* DMC ERR2STATUS register */ 81 #define MORELLO_DMC0_ERR2STATUS_REG UL(0x4E000790) 82 #define MORELLO_DMC1_ERR2STATUS_REG UL(0x4E100790) 83 84 /* DMC memory commands */ 85 #define MORELLO_DMC_MEMC_CMD_CONFIG U(0) 86 #define MORELLO_DMC_MEMC_CMD_READY U(3) 87 88 #endif /* MORELLO_DEF_H */ 89