1 /* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MORELLO_DEF_H 8 #define MORELLO_DEF_H 9 10 /* Non-secure SRAM MMU mapping */ 11 #define MORELLO_NS_SRAM_BASE UL(0x06000000) 12 #define MORELLO_NS_SRAM_SIZE UL(0x00010000) 13 #define MORELLO_MAP_NS_SRAM MAP_REGION_FLAT( \ 14 MORELLO_NS_SRAM_BASE, \ 15 MORELLO_NS_SRAM_SIZE, \ 16 MT_DEVICE | MT_RW | MT_SECURE) 17 18 /* SDS Platform information defines */ 19 #define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8) 20 #define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0) 21 #define MORELLO_SDS_PLATFORM_INFO_SIZE U(18) 22 #define MORELLO_MAX_DDR_CAPACITY U(0x1000000000) 23 #define MORELLO_MAX_SLAVE_COUNT U(16) 24 25 /* SDS BL33 image information defines */ 26 #define MORELLO_SDS_BL33_INFO_STRUCT_ID U(9) 27 #define MORELLO_SDS_BL33_INFO_OFFSET U(0) 28 #define MORELLO_SDS_BL33_INFO_SIZE U(12) 29 30 /* Base address of non-secure SRAM where Platform information will be filled */ 31 #define MORELLO_PLATFORM_INFO_BASE UL(0x06000000) 32 33 /* DMC memory status registers */ 34 #define MORELLO_DMC0_MEMC_STATUS_REG 0x4E000000 35 #define MORELLO_DMC1_MEMC_STATUS_REG 0x4E100000 36 37 #define MORELLO_DMC_MEMC_STATUS_MASK U(7) 38 39 /* DMC memory command registers */ 40 #define MORELLO_DMC0_MEMC_CMD_REG 0x4E000008 41 #define MORELLO_DMC1_MEMC_CMD_REG 0x4E100008 42 43 /* DMC ERR0CTLR0 registers */ 44 #define MORELLO_DMC0_ERR0CTLR0_REG 0x4E000708 45 #define MORELLO_DMC1_ERR0CTLR0_REG 0x4E100708 46 47 /* DMC ECC in ERR0CTLR0 register */ 48 #define MORELLO_DMC_ERR0CTLR0_ECC_EN U(9) 49 50 /* DMC ERR2STATUS register */ 51 #define MORELLO_DMC0_ERR2STATUS_REG 0x4E000790 52 #define MORELLO_DMC1_ERR2STATUS_REG 0x4E100790 53 54 /* DMC memory commands */ 55 #define MORELLO_DMC_MEMC_CMD_CONFIG U(0) 56 #define MORELLO_DMC_MEMC_CMD_READY U(3) 57 58 #endif /* MORELLO_DEF_H */ 59