1 /* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE ULL(0x2A400000) 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ U(50000000) 17 18 #define PLAT_ARM_RUN_UART_BASE ULL(0x2A410000) 19 #define PLAT_ARM_RUN_UART_CLK_IN_HZ U(50000000) 20 21 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 22 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 23 24 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 25 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) 26 27 #define MAX_IO_DEVICES U(3) 28 #define MAX_IO_HANDLES U(4) 29 30 #define PLAT_ARM_FLASH_IMAGE_BASE ULL(0x1A000000) 31 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE ULL(0x01000000) 32 33 #define PLAT_ARM_NVM_BASE ULL(0x1A000000) 34 #define PLAT_ARM_NVM_SIZE ULL(0x01000000) 35 36 #if defined NS_BL1U_BASE 37 #undef NS_BL1U_BASE 38 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) 39 #endif 40 41 /* 42 * There are no non-volatile counters in morello, these macros points 43 * to unused addresses. 44 */ 45 #define SOC_TRUSTED_NVCTR_BASE ULL(0x7FE70000) 46 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0000)) 47 #define TFW_NVCTR_SIZE U(4) 48 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0004)) 49 #define NTFW_CTR_SIZE U(4) 50 51 /* 52 * To access the complete DDR memory along with remote chip's DDR memory, 53 * which is at 4 TB offset, physical and virtual address space limits are 54 * extended to 43-bits. 55 */ 56 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) 57 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) 58 59 #if CSS_USE_SCMI_SDS_DRIVER 60 #define MORELLO_SCMI_PAYLOAD_BASE ULL(0x45400000) 61 #else 62 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE ULL(0x45400000) 63 #endif 64 65 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000) 66 67 /* 68 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 69 * plus a little space for growth. 70 */ 71 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 72 73 /* 74 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 75 */ 76 77 #if USE_ROMLIB 78 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 79 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xE000) 80 #else 81 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) 82 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) 83 #endif 84 85 /* 86 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 87 * little space for growth. 88 */ 89 #if TRUSTED_BOARD_BOOT 90 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 91 #else 92 # define PLAT_ARM_MAX_BL2_SIZE UL(0x14000) 93 #endif 94 95 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 96 97 /******************************************************************************* 98 * MORELLO topology related constants 99 ******************************************************************************/ 100 #define MORELLO_MAX_CPUS_PER_CLUSTER U(2) 101 #define PLAT_ARM_CLUSTER_COUNT U(2) 102 #define PLAT_MORELLO_CHIP_COUNT U(1) 103 #define MORELLO_MAX_CLUSTERS_PER_CHIP U(2) 104 #define MORELLO_MAX_PE_PER_CPU U(1) 105 106 #define PLATFORM_CORE_COUNT (PLAT_MORELLO_CHIP_COUNT * \ 107 PLAT_ARM_CLUSTER_COUNT * \ 108 MORELLO_MAX_CPUS_PER_CLUSTER * \ 109 MORELLO_MAX_PE_PER_CPU) 110 111 /* System power domain level */ 112 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 113 114 /* 115 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 116 * plat_arm_mmap array defined for each BL stage. 117 */ 118 #if IMAGE_BL1 || IMAGE_BL31 119 # define PLAT_ARM_MMAP_ENTRIES U(6) 120 # define MAX_XLAT_TABLES U(7) 121 #else 122 # define PLAT_ARM_MMAP_ENTRIES U(5) 123 # define MAX_XLAT_TABLES U(6) 124 #endif 125 126 /* 127 * Size of cacheable stacks 128 */ 129 #if defined(IMAGE_BL1) 130 # if TRUSTED_BOARD_BOOT 131 # define PLATFORM_STACK_SIZE UL(0x1000) 132 # else 133 # define PLATFORM_STACK_SIZE UL(0x440) 134 # endif 135 #elif defined(IMAGE_BL2) 136 # if TRUSTED_BOARD_BOOT 137 # define PLATFORM_STACK_SIZE UL(0x1000) 138 # else 139 # define PLATFORM_STACK_SIZE UL(0x400) 140 # endif 141 #elif defined(IMAGE_BL2U) 142 # define PLATFORM_STACK_SIZE UL(0x400) 143 #elif defined(IMAGE_BL31) 144 # if SPM_MM 145 # define PLATFORM_STACK_SIZE UL(0x500) 146 # else 147 # define PLATFORM_STACK_SIZE UL(0x400) 148 # endif 149 #elif defined(IMAGE_BL32) 150 # define PLATFORM_STACK_SIZE UL(0x440) 151 #endif 152 153 #define PLAT_ARM_NSTIMER_FRAME_ID U(0) 154 155 #define PLAT_ARM_TRUSTED_ROM_BASE U(0x0) 156 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) /* 128KB */ 157 158 #define PLAT_ARM_NSRAM_BASE ULL(0x06000000) 159 #define PLAT_ARM_NSRAM_SIZE UL(0x00010000) /* 64KB */ 160 161 #define PLAT_CSS_MHU_BASE UL(0x45000000) 162 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 163 #define PLAT_MAX_PWR_LVL U(2) 164 165 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 166 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 167 168 #define MORELLO_DEVICE_BASE ULL(0x08000000) 169 #define MORELLO_DEVICE_SIZE ULL(0x48000000) 170 171 /*Secure Watchdog Constants */ 172 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 173 #define SBSA_SECURE_WDOG_TIMEOUT UL(1000) 174 175 #define MORELLO_MAP_DEVICE MAP_REGION_FLAT( \ 176 MORELLO_DEVICE_BASE, \ 177 MORELLO_DEVICE_SIZE, \ 178 MT_DEVICE | MT_RW | MT_SECURE) 179 180 #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ 181 ARM_DRAM1_BASE, \ 182 ARM_DRAM1_SIZE, \ 183 MT_MEMORY | MT_RW | MT_NS) 184 185 /* GIC related constants */ 186 #define PLAT_ARM_GICD_BASE UL(0x30000000) 187 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 188 #define PLAT_ARM_GICR_BASE UL(0x300C0000) 189 190 /* Number of SCMI channels on the platform */ 191 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 192 193 #endif /* PLATFORM_DEF_H */ 194