1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 #include <plat_arm.h> 9 10 /* 11 * Table of memory regions for different BL stages to map using the MMU. 12 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 13 * of mapping it. 14 */ 15 #ifdef IMAGE_BL1 16 const mmap_region_t plat_arm_mmap[] = { 17 ARM_MAP_SHARED_RAM, 18 V2M_MAP_FLASH0_RW, 19 V2M_MAP_IOFPGA, 20 CSS_MAP_DEVICE, 21 SOC_CSS_MAP_DEVICE, 22 #if TRUSTED_BOARD_BOOT 23 /* Map DRAM to authenticate NS_BL2U image. */ 24 ARM_MAP_NS_DRAM1, 25 #endif 26 {0} 27 }; 28 #endif 29 #ifdef IMAGE_BL2 30 const mmap_region_t plat_arm_mmap[] = { 31 ARM_MAP_SHARED_RAM, 32 V2M_MAP_FLASH0_RW, 33 #ifdef PLAT_ARM_MEM_PROT_ADDR 34 ARM_V2M_MAP_MEM_PROTECT, 35 #endif 36 V2M_MAP_IOFPGA, 37 CSS_MAP_DEVICE, 38 SOC_CSS_MAP_DEVICE, 39 ARM_MAP_NS_DRAM1, 40 #ifdef AARCH64 41 ARM_MAP_DRAM2, 42 #endif 43 #ifdef SPD_tspd 44 ARM_MAP_TSP_SEC_MEM, 45 #endif 46 #ifdef SPD_opteed 47 ARM_MAP_OPTEE_CORE_MEM, 48 ARM_OPTEE_PAGEABLE_LOAD_MEM, 49 #endif 50 {0} 51 }; 52 #endif 53 #ifdef IMAGE_BL2U 54 const mmap_region_t plat_arm_mmap[] = { 55 ARM_MAP_SHARED_RAM, 56 CSS_MAP_DEVICE, 57 CSS_MAP_SCP_BL2U, 58 V2M_MAP_IOFPGA, 59 SOC_CSS_MAP_DEVICE, 60 {0} 61 }; 62 #endif 63 #ifdef IMAGE_BL31 64 const mmap_region_t plat_arm_mmap[] = { 65 ARM_MAP_SHARED_RAM, 66 V2M_MAP_IOFPGA, 67 CSS_MAP_DEVICE, 68 #ifdef PLAT_ARM_MEM_PROT_ADDR 69 ARM_V2M_MAP_MEM_PROTECT, 70 #endif 71 SOC_CSS_MAP_DEVICE, 72 {0} 73 }; 74 #endif 75 #ifdef IMAGE_BL32 76 const mmap_region_t plat_arm_mmap[] = { 77 #ifdef AARCH32 78 ARM_MAP_SHARED_RAM, 79 #ifdef PLAT_ARM_MEM_PROT_ADDR 80 ARM_V2M_MAP_MEM_PROTECT, 81 #endif 82 #endif 83 V2M_MAP_IOFPGA, 84 CSS_MAP_DEVICE, 85 SOC_CSS_MAP_DEVICE, 86 {0} 87 }; 88 #endif 89 90 ARM_CASSERT_MMAP 91