1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <drivers/arm/css/sds.h> 8 #include <lib/smccc.h> 9 #include <lib/utils_def.h> 10 #include <services/arm_arch_svc.h> 11 12 #include <plat/arm/common/plat_arm.h> 13 #include <platform_def.h> 14 15 /* 16 * Table of memory regions for different BL stages to map using the MMU. 17 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 18 * of mapping it. 19 */ 20 #ifdef IMAGE_BL1 21 const mmap_region_t plat_arm_mmap[] = { 22 ARM_MAP_SHARED_RAM, 23 V2M_MAP_FLASH0_RW, 24 V2M_MAP_IOFPGA, 25 CSS_MAP_DEVICE, 26 SOC_CSS_MAP_DEVICE, 27 #if TRUSTED_BOARD_BOOT 28 /* Map DRAM to authenticate NS_BL2U image. */ 29 ARM_MAP_NS_DRAM1, 30 #endif 31 {0} 32 }; 33 #endif 34 #ifdef IMAGE_BL2 35 const mmap_region_t plat_arm_mmap[] = { 36 ARM_MAP_SHARED_RAM, 37 V2M_MAP_FLASH0_RW, 38 #ifdef PLAT_ARM_MEM_PROT_ADDR 39 ARM_V2M_MAP_MEM_PROTECT, 40 #endif 41 V2M_MAP_IOFPGA, 42 CSS_MAP_DEVICE, 43 SOC_CSS_MAP_DEVICE, 44 ARM_MAP_NS_DRAM1, 45 #ifdef __aarch64__ 46 ARM_MAP_DRAM2, 47 #endif 48 #ifdef SPD_tspd 49 ARM_MAP_TSP_SEC_MEM, 50 #endif 51 #ifdef SPD_opteed 52 ARM_MAP_OPTEE_CORE_MEM, 53 ARM_OPTEE_PAGEABLE_LOAD_MEM, 54 #endif 55 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 56 ARM_MAP_BL1_RW, 57 #endif 58 #ifdef JUNO_ETHOSN_TZMP1 59 JUNO_ETHOSN_PROT_FW_RW, 60 #endif 61 {0} 62 }; 63 #endif 64 #ifdef IMAGE_BL2U 65 const mmap_region_t plat_arm_mmap[] = { 66 ARM_MAP_SHARED_RAM, 67 CSS_MAP_DEVICE, 68 CSS_MAP_SCP_BL2U, 69 V2M_MAP_IOFPGA, 70 SOC_CSS_MAP_DEVICE, 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL31 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_IOFPGA, 78 CSS_MAP_DEVICE, 79 #ifdef PLAT_ARM_MEM_PROT_ADDR 80 ARM_V2M_MAP_MEM_PROTECT, 81 #endif 82 SOC_CSS_MAP_DEVICE, 83 ARM_DTB_DRAM_NS, 84 #ifdef JUNO_ETHOSN_TZMP1 85 JUNO_ETHOSN_PROT_FW_RO, 86 #endif 87 {0} 88 }; 89 #endif 90 #ifdef IMAGE_BL32 91 const mmap_region_t plat_arm_mmap[] = { 92 #ifndef __aarch64__ 93 ARM_MAP_SHARED_RAM, 94 #ifdef PLAT_ARM_MEM_PROT_ADDR 95 ARM_V2M_MAP_MEM_PROTECT, 96 #endif 97 #endif 98 V2M_MAP_IOFPGA, 99 CSS_MAP_DEVICE, 100 SOC_CSS_MAP_DEVICE, 101 {0} 102 }; 103 #endif 104 105 ARM_CASSERT_MMAP 106 107 /***************************************************************************** 108 * plat_is_smccc_feature_available() - This function checks whether SMCCC 109 * feature is availabile for platform. 110 * @fid: SMCCC function id 111 * 112 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 113 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 114 *****************************************************************************/ 115 int32_t plat_is_smccc_feature_available(u_register_t fid) 116 { 117 switch (fid) { 118 case SMCCC_ARCH_SOC_ID: 119 return SMC_ARCH_CALL_SUCCESS; 120 default: 121 return SMC_ARCH_CALL_NOT_SUPPORTED; 122 } 123 } 124 125 /* Get SOC version */ 126 int32_t plat_get_soc_version(void) 127 { 128 return (int32_t) 129 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, 130 ARM_SOC_IDENTIFICATION_CODE) | 131 (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK)); 132 } 133 134 /* Get SOC revision */ 135 int32_t plat_get_soc_revision(void) 136 { 137 unsigned int sys_id; 138 139 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 140 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & 141 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); 142 } 143 144 #if CSS_USE_SCMI_SDS_DRIVER 145 static sds_region_desc_t juno_sds_regions[] = { 146 { .base = PLAT_ARM_SDS_MEM_BASE }, 147 }; 148 149 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count) 150 { 151 *region_count = ARRAY_SIZE(juno_sds_regions); 152 153 return juno_sds_regions; 154 } 155 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 156