1*07570d59SYatharth Kochar /* 2*07570d59SYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*07570d59SYatharth Kochar * 4*07570d59SYatharth Kochar * Redistribution and use in source and binary forms, with or without 5*07570d59SYatharth Kochar * modification, are permitted provided that the following conditions are met: 6*07570d59SYatharth Kochar * 7*07570d59SYatharth Kochar * Redistributions of source code must retain the above copyright notice, this 8*07570d59SYatharth Kochar * list of conditions and the following disclaimer. 9*07570d59SYatharth Kochar * 10*07570d59SYatharth Kochar * Redistributions in binary form must reproduce the above copyright notice, 11*07570d59SYatharth Kochar * this list of conditions and the following disclaimer in the documentation 12*07570d59SYatharth Kochar * and/or other materials provided with the distribution. 13*07570d59SYatharth Kochar * 14*07570d59SYatharth Kochar * Neither the name of ARM nor the names of its contributors may be used 15*07570d59SYatharth Kochar * to endorse or promote products derived from this software without specific 16*07570d59SYatharth Kochar * prior written permission. 17*07570d59SYatharth Kochar * 18*07570d59SYatharth Kochar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*07570d59SYatharth Kochar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*07570d59SYatharth Kochar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*07570d59SYatharth Kochar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*07570d59SYatharth Kochar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*07570d59SYatharth Kochar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*07570d59SYatharth Kochar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*07570d59SYatharth Kochar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*07570d59SYatharth Kochar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*07570d59SYatharth Kochar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*07570d59SYatharth Kochar * POSSIBILITY OF SUCH DAMAGE. 29*07570d59SYatharth Kochar */ 30*07570d59SYatharth Kochar 31*07570d59SYatharth Kochar #include <assert.h> 32*07570d59SYatharth Kochar #include <bl_common.h> 33*07570d59SYatharth Kochar #include <desc_image_load.h> 34*07570d59SYatharth Kochar #include <plat_arm.h> 35*07570d59SYatharth Kochar 36*07570d59SYatharth Kochar #if JUNO_AARCH32_EL3_RUNTIME 37*07570d59SYatharth Kochar /******************************************************************************* 38*07570d59SYatharth Kochar * This function changes the spsr for BL32 image to bypass 39*07570d59SYatharth Kochar * the check in BL1 AArch64 exception handler. This is needed in the aarch32 40*07570d59SYatharth Kochar * boot flow as the core comes up in aarch64 and to enter the BL32 image a warm 41*07570d59SYatharth Kochar * reset in aarch32 state is required. 42*07570d59SYatharth Kochar ******************************************************************************/ 43*07570d59SYatharth Kochar int bl2_plat_handle_post_image_load(unsigned int image_id) 44*07570d59SYatharth Kochar { 45*07570d59SYatharth Kochar int err = arm_bl2_handle_post_image_load(image_id); 46*07570d59SYatharth Kochar 47*07570d59SYatharth Kochar if (!err && (image_id == BL32_IMAGE_ID)) { 48*07570d59SYatharth Kochar bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 49*07570d59SYatharth Kochar assert(bl_mem_params); 50*07570d59SYatharth Kochar bl_mem_params->ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 51*07570d59SYatharth Kochar DISABLE_ALL_EXCEPTIONS); 52*07570d59SYatharth Kochar } 53*07570d59SYatharth Kochar 54*07570d59SYatharth Kochar return err; 55*07570d59SYatharth Kochar } 56*07570d59SYatharth Kochar #endif /* JUNO_AARCH32_EL3_RUNTIME */ 57