xref: /rk3399_ARM-atf/plat/arm/board/juno/aarch64/juno_helpers.S (revision fd6007de64fd7e16f6d96972643434c04a77f1c6)
1/*
2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
34#include <cortex_a57.h>
35#include <v2m_def.h>
36#include "../juno_def.h"
37
38
39	.globl	plat_reset_handler
40
41
42	/* --------------------------------------------------------------------
43	 * void plat_reset_handler(void);
44	 *
45	 * For Juno r0:
46	 * - Implement workaround for defect id 831273 by enabling an event
47	 *   stream every 65536 cycles.
48	 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
49	 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
50	 *
51	 * For Juno r1:
52	 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
53	 * Note that:
54	 * - The default value for the L2 Tag RAM latency for Cortex-A57 is
55	 *   suitable.
56	 * - Defect #831273 doesn't affect Juno r1.
57	 * --------------------------------------------------------------------
58	 */
59func plat_reset_handler
60	/* --------------------------------------------------------------------
61	 * Determine whether this code is running on Juno r0 or Juno r1.
62	 * Keep this information in x2.
63	 * --------------------------------------------------------------------
64	 */
65	/* Read the V2M SYS_ID register */
66	mov_imm	x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
67	ldr	w1, [x0]
68	/* Extract board revision from the SYS_ID */
69	ubfx	x1, x1, #V2M_SYS_ID_REV_SHIFT, #4
70	/*
71	 * On Juno R0:  x2 := REV_JUNO_R0 - 1 = 0
72	 * On Juno R1:  x2 := REV_JUNO_R1 - 1 = 1
73	 */
74	sub	x2, x1, #1
75
76	/* --------------------------------------------------------------------
77	 * Determine whether this code is executed on a Cortex-A53 or on a
78	 * Cortex-A57 core.
79	 * --------------------------------------------------------------------
80	 */
81	mrs	x0, midr_el1
82	ubfx	x1, x0, MIDR_PN_SHIFT, #12
83	cmp     w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
84	b.eq	A57
85
86	/* Nothing needs to be done for the Cortex-A53 on Juno r1 */
87	cbz	x2, apply_831273
88	ret
89
90A57:
91	/* --------------------------------------------------------------------
92	 * Cortex-A57 specific settings
93	 * --------------------------------------------------------------------
94	 */
95
96	/* Change the L2 Data RAM latency to 3 cycles */
97	mov	x0, #L2_DATA_RAM_LATENCY_3_CYCLES
98	cbnz	x2, apply_l2_ram_latencies
99	/* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */
100	orr	x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << 		\
101				L2CTLR_TAG_RAM_LATENCY_SHIFT)
102apply_l2_ram_latencies:
103	msr     L2CTLR_EL1, x0
104
105	/* Juno r1 doesn't suffer from defect #831273 */
106	cbnz	x2, ret
107
108apply_831273:
109	/* --------------------------------------------------------------------
110	 * On Juno r0, enable the event stream every 65536 cycles
111	 * --------------------------------------------------------------------
112	 */
113	mov     x0, #(0xf << EVNTI_SHIFT)
114	orr     x0, x0, #EVNTEN_BIT
115	msr     CNTKCTL_EL1, x0
116ret:
117	isb
118	ret
119endfunc plat_reset_handler
120